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| 1. general description the pn7462 family is a family of 32-bit arm cortex-m0-based nfc microcontrollers offering high performance and low power cons umption. it has a simple instruction set and memory addressing along with a reduced code size compared to existing architectures. pn7462 family offers all in one solutions, wit h features such as nfc, microcontroller, optional contact smart card reader, and software in a single chip. it operates at cpu frequencies of up to 20 mhz. the family includes the following deriva tives to fit every specific need: ? pn7462: nfc microcontroller, 160 kb fl ash memory, and an iso 7816/emvco contact interface ? pn7362: nfc microcontroller with 160 kb flash memory ? pn7360: nfc microcontroller with 80 kb flash memory the peripheral complement of the pn7462 family microcontrollers includes 160/80 kb of flash memory, 12 kb of sram data memory and 4 kb eeprom. it also includes one host interface with either high-speed mode i 2 c-bus, spi, usb or high-speed uart, and two master interfaces, spi and fast-mode plus i 2 c-bus. four general-purpose counter/timers, a random number generator, one crc coprocessor and up to 21 general-purpose i/o pins are also available. the pn7462 family nfc microc ontrollers offer a one chip solution to build contactless applications. it is equipped with a highly integrated high-power output nfc-ic for contactless communication at 13.56 mhz ena bling emv-compliance on rf level, without additional external active components. pn7462 family supports the following operating modes: ? iso/iec 14443-a and b, mifare ? jis x 6319-4 (compara ble with felica scheme) ? iso/iec 15693, icode, iso/iec 18000-3 mode 3 ? nfc protocols - tag reader/writer, p2p ? iso/iec 14443- type a card emulation ? emvco compliance by integrating an iso/iec 7816 interface on a single chip in the pn7462, it provides a solution for dual interface smart card readers. pn7462 contact interface offers a high level of security for the card by performing current limiting, short-circuit detection, esd PN746X_736x nfc cortex-m0 mi crocontroller rev. 3.1 ? 5 april 2016 369231 product data sheet company public
PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 2 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller protection as well as supply su pervision. an additional uart output is also implemented to address applications where more than one contact card slot is needed. it enables an easy connection to multiple smart card slot interfaces like tda8026. the v cc is regulated at 5 v, 3 v, and 1.8 v. pn7462 provides thermal and short-circuit protection on all card contacts. it also pr ovides automatic activation and deactivation sequences initiated by software or hardware. the sequences are activated or deactivated in the event of short-circuit, card removal, and overheating. 2. features and benefits 2.1 integrated contact interface frontend ? class a, b, and c cards can work on 1.8 v, 3 v, and 5 v supply ? specific iso uart, variable baud rate through frequency or division ratio programming, error management at character level for t = 0, and extra guard time register ? dc-to-dc converter for class a support starting at 3 v, and class b support starting at 2.7 v ? thermal and short-circuit protection on contact cards ? automatic activation and deactivation sequen ce, initiated by software or by hardware in case of short-circuit, card removal, overheating, and v dd or v dd drop-out ? enhanced esd protection (> 8 kv) ? iso/iec 7816 compliant ? emvco 4.3 compliant ? clock generation up to 13.56 mhz ? synchronous card support ? possibility to extend the number of contac t interfaces, with the addition of slot extenders such as tda8026 2.2 integrated contactless interface frontend ? high rf output power frontend ic for transfer speed up to 848 kbit/s ? nfc ip1 and nfc ip2 support ? full nfc tag support (type 1, type 2, type 3, type 4a and type 4b) ? p2p active and passive, target and initiator ? card emulation iso14443 type a ? iso/iec 14443 type a and type b ? mifare classic card ? iso/iec 15693, and iso/iec 18000-3 mode 3 ? low power card detection ? dynamic power control (dpc) support ? compliance with emv contactless protocol specification ? compliance with nfc standards 2.3 cortex-m0 microcontroller ? processor core PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 3 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? arm cortex: 32-bit m0 processor ? built-in nested vectored interrupt controller (nvic) ? non-maskable interrupt ? 24-bit system tick timer ? running frequency of up to 20 mhz ? clock management to enable low power consumption ? memory ? flash: 160 kb ? sram: 12 kb ? eeprom: 4 kb ? 40 kb boot rom included, including us b mass storage primary bootloader for code download ? debug option ? serial wire debug (swd) interface ? peripherals ? host interface: ? usb 2.0 full speed with usb 3. 0 hub connection capability ? hsuart for serial communication, supporting standards speeds from 9600 baud to 115200 baud, and faster speed up to 1.288 mbit/s ? spi with half duplex and full duplex capability with speeds up to 7 mbit/s ? i 2 c supporting standard mode, fast mode and high-speed mode with multiple address support ? master interface: ? spi with half duplex capability from 1 mbit/s to 6.78 mbit/s ? i 2 c supporting standard mode, fast mode, fast mode plus and clock stretching ? up to 21 general-purpose i/o (gpio) with configurable pull-up/ pull-down resistors ? gpio1 to gpio12 can be used as edge and level sensitive interrupt sources ? power ? two reduced power modes: standby mode and hard power-down mode ? supports suspend mode for usb host interface ? processor wake-up from hard power-down mode, standby mode, suspend mode via host interface, contact card in terface, gpios, rf field detection ? integrated pmu to ad just internal regulators automatically, to minimize the power consumption during all possible power modes ? power-on reset ? rf supply: external, or using an integrat ed ldo (tx ldo, configurable with 3 v, 3.3 v, 3.6 v, 4.5 v, and 4.75 v) ? pad voltage supply: external 3.3 v or 1.8 v, or using an integrated ldo (3.3 v supply) ? integrated contact interface voltage regulation for 1.8 v, 3 v, and 5 v card supply, including a dc-to-dc converter for supporting class a and class b cards ? timers ? four general-purpose timers ? programmable watchdog timer (wdt) ? crc coprocessor PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 4 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? random number generator ? clocks ? crystal oscillator at 27.12 mhz ? dedicated pll at 48 mhz for the usb ? integrated hfo 20 mhz and lfo 365 khz ? general ? hvqfn64 package ? temperature range: ? 40 ? c to +85 ? c 3. applications ? physical access control ? gaming ? usb nfc reader, including dual interface smart card readers ? home banking, payment readers emvco compliant ? high integration devices ? nfc applications 4. quick reference data table 1. quick reference data operating range: ? 40 ? c to +85 ? c unless specified; contact interface: v ddp(vbusp) = v ddp(vbus) ; contactless interface: internal ldo not used symbol parameter conditions min typ max unit v ddp(vbus) power supply voltage on pin vbus card emulation, passive target (plm) 2.3 - 5.5 v all rf modes; class b and class c contact interface support 2.7 - 5.5 v all rf modes; class a, class b and class c contact interface support 3- 5.5v v dd(pvdd) pvdd supply voltage 1.8 v 1.65 1.8 1.95 v 3.3 v 3 3.3 3.6 v i ddp(vbus) power supply current on pin vbus in hard power-down mode; t=25 ?c; v ddp(vbus) = 5.5 v; rst_n = 0 -1218 ? a stand by mode; t = 25 ?c; v ddp(vbus) = 3.3 v; external pvdd ldo used -18- ? a stand by mode; t = 25 ?c; v ddp(vbus) = 5.5 v; internal pvdd ldo used -55- ? a suspend mode, usb interface; v ddp(vbus) = 5.5 v; external pvdd supply; t = 25 ?c - 120 250 a PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 5 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 5. ordering information the pn7462 family includes the following products: pn7462au: full feature set and memory available pn7362au: full memory availa ble, no contact interface pn7360au: memory limited to 80 kb, and no contact interface. the table below lists the ordering information for these three products. i dd(tvdd) tvdd supply current on pin tvdd_in; maximum supported current by the contactless interface --250ma v cc supply voltage contact card class a; i cc < 60 ma 4.75 5 5.25 v class b; i cc < 50 ma 2.85 3 3.15 v class c; i cc < 30 ma 1.71 1.8 1.89 v i cc supply current contact card class a cards - - 60 ma class b cards - - 55 ma class c cards - - 35 ma p max maximum power dissipation - - 1050 mw t amb ambient temperature jedec pcb ? 40 - +85 ?c table 1. quick reference data ?continued operating range: ? 40 ? c to +85 ? c unless specified; contact interface: v ddp(vbusp) = v ddp(vbus) ; contactless interface: internal ldo not used symbol parameter conditions min typ max unit table 2. ordering information type number package name description version pn7462auhn hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 ?? 9 ?? 0.85 mm sot804-4 pn7362auhn hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 ?? 9 ?? 0.85 mm sot804-4 pn7360auhn hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 ?? 9 ?? 0.85 mm sot804-4 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 6 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 6. block diagram fig 1. block diagram d d d $ 5 0 & 2 5 7 ( ; 0 v \ v w h p e x v v o d y h v o d y h v o d y h p d v w h u p d v w h u p d v w h u v o d y h 6 5 $ 0 n % ( ( 3 5 2 0 n % $ + % / , 7 ( ) / $ 6 + n % 5 2 0 n % & 2 ' ( 3 $ 7 & + $ + % 7 2 $ 3 % % 0 $ + % % 5 , ' * ( + 2 6 7 , 1 7 ( 5 ) $ & ( 6 8 6 % + 6 8 6 3 , , & & / , ) 6 3 , 0 $ 6 7 ( 5 , & 0 $ 6 7 ( 5 5 1 * 3 2 : ( 5 & / 2 & . $ 1 ' 5 ( 6 ( 7 * 3 , 2 ; 7 $ / 7 , 0 ( 5 6 7 , 0 ( : $ 7 & + ' 2 * 3 0 8 & 5 & , 2 $ 8 ; & 7 , ) , 6 2 8 $ 5 7 0 $ , 1 / ' 2 3 9 ' ' / ' 2 7 ; / ' 2 9 & & / ' 2 6 & / ' 2 7 ( 0 3 ( 5 $ 7 8 5 ( 6 ( 1 6 2 5 & / 2 & . * ( 1 ( 5 $ 7 2 5 6 + ) 2 / ) 2 8 6 % 3 / / ' & ' & $ + % / , 7 ( % 8 ) ) ( 5 0 $ 1 $ * ( 0 ( 1 7 6 : ' PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 7 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin configuration 3 1 $ 8 7 u d q v s d u h q w w r s y l h z 7 ; 6 : ' , 2 * 3 , 2 7 9 ' ' b , 1 6 : ' & / . $ 1 7 , 5 4 $ 1 7 ' : / b 5 ( 4 7 9 ' ' b 2 8 7 ' 9 ' ' 9 8 3 b 7 ; 3 9 ' ' b , 1 9 ' ' $ 7 ; b ' ; 7 $ / $ 7 ; b & ; 7 $ / $ 7 ; b % 5 6 7 b 1 $ 7 ; b $ 9 % 8 6 3 5 ( 6 3 9 ' ' b 2 8 7 , 1 7 b $ 8 ; * 1 ' 3 , 2 b $ 8 ; 6 $ 0 & / . b $ 8 ; 6 & 9 ' ' o & 0 b 6 ' $ 9 % 8 6 3 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 * 3 , 2 5 ; 1 5 ; 3 9 0 , ' 7 ; 7 9 6 6 , & 0 b 6 & / 6 3 , 0 b 0 , 6 2 6 3 , 0 b 0 2 6 , 6 3 , b 6 & / . 6 3 , 0 b 6 6 1 3 9 ' ' b 0 b , 1 8 6 % b 9 % 8 6 , 2 $ 8 ; $ 8 ; * 1 ' & & / . 5 6 7 9 & & 9 8 3 6 $ 3 w h u p l q d o l q g h [ d u h d d d d table 3. pin description symbol pin description i2cm_sda 1 i 2 c-bus serial data i/o master/gpio13 clk_aux 2 auxiliary card contact clock/gpio14 io_aux 3 auxiliary card contact i/o/gpio15 int_aux 4 auxiliary card contact interrupt/gpio16 pres 5 card presence atx_a 6 spi slave select input (nss_s)/i 2 c-bus serial clock input (scl_s)/hsuart rx atx_b 7 spi slave data input (mosi_s)/i 2 c-bus serial data i/o (sda_s)/hsuart tx atx_c 8 usb d+/spi slave data output (miso_s)/i 2 c-bus address bit0 input/hsuart rts atx_d 9 usb d-/spi clock input (sck_s)/i 2 c-bus address bit1 input/hsuart cts pvdd_in 10 pad supply voltage input dvdd 11 digital core logic supply voltage input PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 8 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller dwl_req 12 entering in download mode irq 13 interrupt request output swdclk 14 sw serial debug line clock swdio 15 sw serial debug line input/output gpio1 16 general-purpose i/o/ spi master select2 output gpio2 17 general-purpose i/o gpio3 18 general-purpose i/o gpio4 19 general-purpose i/o gpio5 20 general-purpose i/o gpio6 21 general-purpose i/o gpio7 22 general-purpose i/o gpio8 23 general-purpose i/o gpio9 24 general-purpose i/o gpio10 25 general-purpose i/o gpio11 26 general-purpose i/o gpio12 27 general-purpose i/o rxn 28 receiver input rxp 29 receiver input vmid 30 receiver reference voltage input tx2 31 antenna driver output tvss 32 ground for antenna power supply tx1 33 antenna driver output tvdd_in 34 antenna driver supply voltage input ant1 35 antenna connection for load modulation in card emulation and p2p passive target modes ant2 36 antenna connection for load modulation in card emulation and p2p passive target modes tvdd_out 37 antenna driver supply, output of tx_ldo vup_tx 38 supply of the contactless tx_ldo vdd 39 1.8 v regulator output for digital blocks xtal1 40 27.12 mhz clock input for crystal xtal2 41 27.12 mhz clock input for crystal rst_n 42 reset pin vbus 43 main supply voltage input of microcontroller pvdd_out 44 output of pvdd_ldo for pad voltage supply gndp 45 ground for the contact interface sam 46 dc-to-dc converter connection scvdd 47 input ldo for dc-to-dc converter vbusp 48 main supply for the contact interface sap 49 dc-to-dc converter connection vup 50 reserved; connected to gnd through a decoupling capacitance vcc 51 card supply output of contact interface rst 52 reset pin of contact interface table 3. pin description ?continued symbol pin description PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 9 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8. functional description 8.1 arm cortex-m0 microcontroller the pn7462 is an arm cortex-m0-based 32-bit microcontroller, optimized for low-cost designs, high energy efficiency, and simple instruction set. the cpu operates on an internal clock, which can be configured to provide frequencies such as 20 mhz, 10 mhz, and 5 mhz. the peripheral complement of the pn7462 in cludes a 160 kb flash memory, a 12 kb sram, and a 4 kb eeprom. it also includes one configurable host interface (fast-mode plus and high-speed i 2 c, spi, hsuart, and usb), two mast er interfaces (fast-mode plus i 2 c, spi), four timers, 12 general-purpose i/o pins, one iso/iec 7816 contact card interface, and one 13.56 mhz contactless interface. 8.2 memories 8.2.1 on-chip flash programming memory the pn7462 contains 160 kb on-chip flash program memory. the flash can be programmed using in-system programming (isp) or in-application programming (iap) via the on-chip bootloader software. the flash memory is divided into two instances of 80 kb each, with each sector consisting of individual pages of 64 bytes. 8.2.1.1 memory mapping the flash memory mapping is described in figure 3 . clk 53 clock pin of contact interface gndc 54 ground pin of contact interface aux1 55 c4 card i/o pin of contact interface aux2 56 c8 card i/o pin of contact interface io 57 card i/o usb_vbus 58 used for usb vbus detection pvdd_m_in 59 pad supply voltage input for master interfaces spim_ssn 60 spi master select 1 output/gpio17 spi_sclk 61 spi master clock output/gpio18 spim_mosi 62 spi master data output/gpio19 spim_miso 63 spi master data input/gpio20 i2cm_scl 64 i 2 c-bus serial clock output master/gpio21 table 3. pin description ?continued symbol pin description PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 10 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.2.2 eeprom the pn7462 embeds 4 kb of on-chip by te-erasable and byte -programmable eeprom data memory. the eeprom can be programmed using in-system programming (isp). 8.2.2.1 memory mapping 8.2.3 sram the pn7462 contains a total of 12 kb on-chip static ram memory. fig 3. flash me mory mapping d d d [ $ ) ) ) [ $ ) ) [ x v h u d s s o l f d w l r q . % \ w h v . % \ w h v 5 ( 6 ( 5 9 ( ' [ ) ) ) [ x v h u d s s o l f d w l r q 3 1 3 1 ) / $ 6 + . % \ w h v fig 4. eeprom memory mapping d d d [ ) ) ) [ [ x v h u v s d f h . % \ w h v % \ w h v 5 ( 6 ( 5 9 ( ' PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 11 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.2.3.1 memory mapping the sram memory mapping is shown in figure 5 . 8.2.4 rom the pn7462 contains 40 kb of on-chip rom memory. the on-chip rom contains bootloader, usb mass storage primary download and the following application programming interfaces (apis): ? in-application programming (iap) support for flash ? lifecycle management of debug interface, code write protection of flash memory and usb mass storage primary download ? usb descriptor configuration ? configuration of time-out and source of pad supply 8.2.5 memory map the pn7462 incorporates several distinct memory regions. figure 6 shows the pn7462 memory map, from the user program perspective, following reset. the apb peripheral area is 512 kb in size, and is divided to allow up to 32 peripherals. only peripherals from 0 to 15 are accessible. each peripheral is a llocated 16 kb, which simplifies the address deco ding for the peripherals. apb memory map is described in figure 7 . fig 5. sram memory mapping 5 $ 0 b 6 \ v b ( q g [ ) ) ) d d d 5 $ 0 b 6 \ v b 6 w d u w [ ) 5 $ 0 8 6 ( 5 5 : % \ w h v % \ w h v % \ w h v 5 $ 0 b 6 < 6 7 ( 0 5 ( 6 ( 5 9 ( ' 5 ( 6 ( 5 9 ( ' 5 $ 0 b 8 v h u b 6 w d u w [ 5 $ 0 b 8 v h u b 5 2 b 6 w d u w [ PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 12 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller fig 6. pn7462 memory map * % [ ) ) ) [ [ [ ) ) ) [ [ ) ) ) [ [ $ ) ) ) [ [ ) ) ) ) [ [ ( ) ) ) ) ) ) [ ( [ ) ) ) ) ) ) ) ) 5 ( 6 ( 5 9 ( ' 5 ( 6 ( 5 9 ( ' ( ( 3 5 2 0 5 ( * 5 ( 6 ( 5 9 ( ' 0 % 0 % * % 5 ( 6 ( 5 9 ( ' 5 ( 6 ( 5 9 ( ' 3 5 , 9 $ 7 ( 3 ( 5 , 3 + ( 5 $ / % 8 6 $ 3 % 3 ( 5 , 3 + ( 5 $ / n % ) / $ 6 + n % ( ( 3 5 2 0 n % 6 5 $ 0 n % 5 2 0 d d d 0 % 5 ( 6 ( 5 9 ( ' 5 ( 6 ( 5 9 ( ' PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 13 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.3 nested vectored inte rrupt controller (nvic) cortex-m0 includes a nested vectored interrupt controller (nvic). the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. 8.3.1 nvic features ? system exceptions and peripheral interrupts control ? support 32 vectored interrupts ? four interrupt priority levels with ha rdware priority level masking ? one non-maskable interrupt (nmi) connected to the watchdog interrupt ? software interr upt generation 8.3.2 interrupt sources the following table lists the interrupt sources available in the pn7462 microcontroller. fig 7. apb memory map d d d $ 3 % , ' $ 3 % , ) q d p h 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g & r q q h f w h g , 3 5 h v h u y h g 6 3 , 0 $ 6 7 ( 5 b $ 3 % 6 3 , 0 d v w h u , ) , & 0 $ 6 7 ( 5 b $ 3 % , & 0 d v w h u , ) 5 h v h u y h g 8 6 % b $ 3 % + r v w , ) 8 6 % , 3 3 & 5 b $ 3 % 3 r z h u & o r f n 5 h v h w 0 r g x o h , 3 + 2 6 7 b $ 3 % + r v w , ) , & 6 3 , + 6 8 % x i 0 j w , 3 7 , 0 ( 5 6 b $ 3 % 7 l p h u , 3 5 1 * b $ 3 % 5 1 * , 3 & 7 8 $ 5 7 b $ 3 % & r q w d f w 8 $ 5 7 , 3 & / 2 & . * ( 1 b $ 3 % & o r f n * h q p r g x o h & 5 & b $ 3 % & 5 & , 3 3 0 8 b $ 3 % 3 0 8 p r g x o h v & / b $ 3 % & r q w d f w o h v v , 3 [ [ [ [ & [ [ [ [ & [ [ [ [ & [ [ [ [ & [ [ w r table 4. interrupt sources eirq# source description 0 timer 0/1/2/3 general-purpose timer 0/1/2/3 interrupt 1 - reserved 2 clif contactless interface module interrupt 3 eectrl eeprom controller 4 - reserved 5 - reserved 6 host if tx or rx buffer from i 2 c, spi, hsu, or usb module 7 contact if iso7816 contact module interrupt PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 14 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] the nmi is not available on an external pin. 8 - reserved 9 pmu power management unit (temperature sensor, over current, overload, and vbus level) 10 spi master tx or rx buffer from spi master module 11 i 2 c master tx or rx buffer from i 2 c master module 12 pcr high temperature from temperature se nsor 0 and 1; interrupt to cpu from pcr to indicate wake-up from su spend mode; out of standby; out of suspend; event on gpios configured as inputs 13 pcr interrupt common gpio1 to gpio12 14 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio1 15 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio2 16 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio3 17 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio4 18 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio5 19 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio6 20 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio7 21 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio8 22 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio9 23 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio10 24 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio11 25 pcr interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) gpio12 26 - reserved 27 - reserved 28 - reserved 29 - reserved 30 - reserved 31 - reserved nmi [1] wdt watchdog interrupt is connected to the non-maskable interrupt pin table 4. interrupt sources ?continued eirq# source description PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 15 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.4 gpios the pn7462 has 12 general-purpose i/o (gpio) with configurable pull-up and pull-down resistors, plus nine additional gpios multiplexed with spi master, i 2 c-bus master and aux pins. pins can be dynamically configured as inputs or outputs. gpio read/write are made by the fw using dedicated registers that allow reading, setting or clearing inputs. the value of the output register can be read back, as well as the current state of the input pins. 8.4.1 gpio features ? dynamic configuration as input or output ? 3.3 v and 1.8 v signaling ? programmable weak pull-up and weak pull-down ? independent interrupts for gpio1 to gpio12 ? interrupts: edge or level sensitive ? gpio1 to gpio12 can be programmed as wake-up sources ? programmable spike filter (3 ns) ? programmable slew rate (3 ns and 10 ns) ? hysteresis receiver with disable option 8.4.2 gpio configuration the gpio configuration is done through the pcr module (power, clock, and reset). 8.4.3 gpio interrupts gpio1 to gpio12 can be programmed to generate an interrupt on a level, a rising or falling edge or both. 8.5 crc engine 16/32 bits the pn7462 has a configurable 16/32-bit parallel crc co-processor. the 16-bit crc is compliant to x.25 (crc-cci tt, iso/iec 13239) standard with a generator polynome of: the 32-bit crc is compliant to the ethernet/aal5 (ieee 802.3) standard with a generator polynome of: crc calculation is performed in parallel, meaning that one crc calculation is performed in one clock cycle. the standard crc 32 polynome is complia nt with fips140-2. note : no final xor calculation is performed . following are the crc engine features: ? configurable crc preset value ? selectable lsb or msb first gx ?? x 16 x 12 x 5 1 +++ = gx ?? x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ = PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 16 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? crc 32 calculation based on 32-bit, 16-bit, and 8-bit words ? crc16 calculation based on 32-bit, 16-bit, and 8-bit words ? supports bit order reverse 8.6 random number generator (rng) the pn7462 integrates a random number generator. it consists of an analog true random number generator (trng), and a digital pseudo random number generator (prng). the trng is used for loading a new seed in the prng. the random number generator features: ? 8-bit random number ? compliant with fips 140-2 ? compliant with bsi ais20 and sp800-22 8.7 master interfaces 8.7.1 i 2 c master interface the pn7462 contains one i 2 c master and one i 2 c slave controller. this chapter describes the master interface. for more information on the i 2 c slave controller, refer to section 8.8.2 . the i 2 c-bus is bidirectional for inter-ic control using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice has a unique address. the device can operate either as a receive- only device (such as lcd driver) or a transmitter with the capability to both receive and send information (such as memory). 8.7.1.1 i 2 c features the i 2 c master interface supports the following features: ? standard i 2 c compliant bus interface with open-drain pins ? standard-mode, fast mode and fast mode plus (up to 1 mbit/s). ? support i 2 c master mode only. ? programmable clocks allowing versatile rate control. ? clock stretching ? 7-bit and 10-bit i 2 c slave addressing ? ldm/stm instruction support ? maximum data frame size up to 1024 bytes 8.7.2 spi interface the pn7462 contains one spi master controller and one spi slave controller. the spi master controller transmits the data from the system ram to the spi external slaves. similarly, it receives data from the spi external slaves and stores them into the system ram. it can compute a crc for rece ived frames and automatically compute and append crc for outgoing frames (optional feature). PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 17 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.7.2.1 spi features the spi master interface provides the following features: ? spi master interface: synchronous, half-duplex ? supports motorola spi frame formats only (spi block guide v04.0114 (freescale) specification) ? maximum spi data rate of 6.78 mbit/s ? multiple data rates such as 1, 1.51, 2. 09, 2.47, 3.01, 4.52, 5.42 and 6.78 mbit/s ? up to two slave select with selectable polarity ? programmable clock polarity and phase ? supports 8-bit transfers only ? maximum frame size: 511 data bytes payload + 1 crc byte ? optional 1 byte crc calculation on all data of tx and rx buffer ? ahb master interface for data transfer 8.8 host interfaces the pn7462 embeds four different interfac es for host connection: usb, hsuart, i 2 c, and spi. the four interfaces share the buffer manager and the pins; see ta b l e 5 . the interface selection is done by confi guring the power clock reset (pcr) registers. note: the host interface pins should not be kept floating. 8.8.1 high-speed uart the pn7462 has a high-speed uart which can operate in slave mode only. following are the hsuart features: ? standard bit-rates are 9600, 19200, 38400, 57600, 115200, and up to 1.288 mbit/s ? supports full duplex communication ? supports only one operational mode: start bit, 8 data bits (lsb), and stop bits ? the number of ?stop bits? programmable for rx and tx is 1 stop bit or 2 stop bits ? configurable length of eof (1-bit to 122-bits) table 5. pin description for host interface name spi i 2 c usb hsu atx_a nss_s scl_s - hsu_rx atx_b mosi_s sda_s - hsu_tx atx_c miso_s i 2 c_adr0 dp hsu_rts_n atx_d sck_s i 2 c_adr1 dm hsu_cts_n PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 18 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.8.2 i 2 c host interface controller the pn7462 contains one i 2 c master and one i 2 c slave controller. this section describes the slave interface used for host communi cation. for more information on the i 2 c master controller, refer to section 8.7.1 . the i 2 c-bus is bidirectional and uses only two wires: a serial clock line (scl) and a serial data line (sda). i 2 c standard mode (100 kbit/s), fast mode (400 kbit/s and up to 1 mbit/s), and high-speed mode (3.4 mbit/s) are supported. 8.8.2.1 i 2 c host interface features the pn7462 i 2 c slave interface supports the following features: ? support slave i 2 c bus ? standard mode, fast mode (extended to 1 mbit/s support), and high-speed modes ? supports 7-bit addressing mode only ? selection of the i 2 c address done by two pins ? it supports multiple addresses ? the upper bits of the i 2 c slave address are hard-coded. the value corresponds to the nxp identifier for i 2 c blocks. the value is 01010xxb. ? general call (software reset only) ? software reset (in standard mode and fast mode only) table 6. hsuart baudrates bit rate (kbd) 9.6 19.2 38.4 57.6 115.2 230.4 460.8 921.6 1288 k table 7. i 2 c interface addressing i 2 c_adr1 i 2 c_adr0 i 2 c address (r/w = 0, write) i 2 c address (r/w = 0, read) 000 ?? 28 0 ? 28 010 ? 29 0 ??? 29 100 ? 2a 0 ? 2a 110 ? 2b 0 ? 2b PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 19 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.8.3 spi host/slave interface the pn7462 host interface can be used as spi slave interface. the spi slave controller operates on a four wire ssi: master in slav e out (miso), master out slave in (mosi), serial clock (sck), and not slave select (nss). the spi slave select polarity is fixed to positive polarity. 8.8.3.1 spi host interface features the spi host/slave interface has the following features: ? spi speeds up to 7 mbit/s ? slave operation only ? 8-bit data format only ? programmable clock polarity and phase ? spi slave select polarity sele ction fixed to positive polarity ? half-duplex in hdll mode ? full-duplex in native mode if no data is available, the miso line is kept idle by making all the bits high (0xff). toggling the nss line indicates a new frame. note : programmable echo-back operation is not supported. 8.8.4 usb interface the universal serial bu s (usb) is a 4-wire bus that s upports communication between a host and up to 127 peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot-plugging and dynamic configuration of devices. the host controller initiates all transactions. the pn7462 usb interface consists of a full- speed device controller with on-chip phy (physical layer) fo r device functions. 8.8.4.1 full speed usb device controller the pn7462 embeds a usb device peripheral, compliant with usb 2.0 specification, full speed. it is interoperable with usb 3.0 host devices. the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, and endpoint buffer memory. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. table 8. spi configuration connection cpha switch: clock phase: defines the sampling edge of mosi data ? cpha = 1: data are sampled on mosi on the even clock edges of sck, after nss goes low ? cpha = 0: data are sampled on mosi on th e odd clock edges of sck, after nss goes low cpol switch: clock polarity ? ifsel1 = 0: the clock is idle low, and the first valid edge of sck is a rising one ? ifsel1 = 0: the clock is idle high, and the first valid edge of sck is a falling one PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 20 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller the status of a completed usb transfer or erro r condition is indicated via status registers. if enabled, an interrupt is generated. following are the usb interface features: ? fully compliant with usb 2.0 specification (full speed) ? dedicated usb pll available ? supports 14 physical (7 logical) endpoints including one control endpoint ? each non-control endpoint supports bulk, interrupt, or isochronous endpoint types ? single or double buffering allowed ? support wake-up from suspend mode on usb activity and remote wake-up ? soft-connect supported 8.9 contact interface the pn7462 integrates an iso/iec 7816 interface to enable the communication with a contact smart card. it does not require addition of an external contact frontend for reading payment cards, sam for secure ap plications, etc. it offers a hi gh level of security for the card by performing current limitation, short- circuit detection, esd protection as well as supply supervision. pn7462 also offers the possibility to extend th e number of contact inte rfaces available. it uses an i/o auxiliary interfac e to connect a slot extension (tda8035 - 1 sl ot, tda8020 - 2 slots, and tda8026 - 5 slots). ? class a (5 v), class b (3 v), and cl ass c (1.8 v) smart card supply ? protection of smart card ? three protected half-duplex bidirectional buffered i/o lines (c4, c7, and c8) ? compliant with iso/iec 7816 and emvco 4.3 standards 8.9.1 contact interface features and benefits ? protection of the smart card ? thermal and current limitation in the event of short-circuit (pins i/o, v cc ) ? v cc regulation: 5 v, 3 v, and 1.8 v ? automatic deactivation initiated by hardware in the event of a short-circuit, card take-off, overheating, falling of pn7462 supply ? enhanced card-side electrostatic discharge (esd) protection of greater than 8 kv ? support of class a, class b, and class c contact smart cards ? dc-to-dc converter for v cc generation to enable support of class a and class b cards with low input voltages ? built-in debouncing on card presence contact ? compliant with iso/iec 7816 and emvco 4.3 standards ? card clock generation up to 13.56 mhz usin g external crystal oscillator (27.12 mhz); provides synchronous frequency changes of f xtal / 2, f xtal / 3, f xtal / 4, f xtal / 5, f xtal / 6, f xtal / 8, and f xtal / 16 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 21 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? specific iso/iec uart with apb access for automatic conv ention processing, variable baudrate through frequency or division ratio programming, error management at character level for t = 0 and extra guard time register ? fifo 1 character to 32 characters in both reception and transmission mode ? parity error counter in reception mode and transmission mode with automatic retransmission ? cards clock stop (at high or low level) ? automatic activation and deactivation sequence through a sequencer ? supports the asynchronous protocols t = 0 and t = 1 in accordance with iso/iec 7816 and emv ? versatile 24-bit time-out counter for an swer to reset (atr ) and waiting times processing ? specific elementary time unit (etu) coun ter for block guard time (bgt); 22 etu in t = 1 and 16 etu in t = 0 ? supports synchronous cards 8.9.2 voltage supervisor the pn7462 integrates a voltage monitor to ensu re that sufficient voltage is available for the contact interface; see section 8.15.4 and section 9.1.3 . in order to provide the right voltage needed for the various iso/iec 7816 contact card classes (a, b, or c), the following voltages are needed: ? v ddp(vbusp) > 2.7 v for support of class b and class c contact cards ? v ddp(vbusp) > 3 v for support of class a contact cards ? remark: to support class a cards, dc-to-dc converter is used in doubler mode. to support class b cards with v ddp(vbusp) < 3.9 v, dc-to-dc conver ter is used in doubler mode. to support class b cards with v ddp(vbusp) > 3.9 v, dc-to-dc converter is used in follower mode. figure 8 shows the classes that are supported, depending on v ddp(vbusp) . fig 8. v ddp(vbus) , supported contact cards classes, and card deactivation d d d 9 9 9 9 ' ' 3 9 % 8 6 3 f o d v v $ f d u g v f o d v v % f d u g v 9 ' ' 3 9 % 8 6 3 w k u h v k r o g y d o x h f o d v v & f d u g v ' & w r ' & f r q y h u w h u q h h g h g l q g r x e o h u p r g h ' & w r ' & f r q y h u w h u q h h g h g l q i r o o r z h u p r g h f d u g g h d f w l y d w l r q w r e h s h u i r u p h g z k h q 9 ' ' 3 9 % 8 6 3 l v j r l q j e h o r z w k h w k u h v k r o g y d o x h PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 22 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller when the v ddp(vbusp) is going below the threshold value, in the one of the conditions indicated below, a card deactivation is performed: ? class a card activated, and v ddp(vbusp) going below 3 v ? class b card activated, and v ddp(vbusp) going below 3.9 v (dc-to-dc converter in follower mode) ? class b card activated, and v ddp(vbusp) going below 2.7 v (dc-to-dc converter in doubler mode) ? class c card activated, and v ddp(vbusp) going below 2.7 v the vbusp voltage monitor can be configured so that an automatic ?card deactivation? sequence is performed automatically when v ddp(vbusp) is going below the threshold value. 8.9.3 clock circuitry the card clock is generated from the crystal oscillator, connected on the pin xtal1 and xtal2. the card frequency is configured through the contact interface registers. the following value can be chosen: f xtal /2, f xtal / 3, f xtal / 4, f xtal / 5, f xtal / 6, f xtal / 8, and f xtal /16. it is possible to put the card clock to a logical level 0 or 1 (clock stop feature). the duty cycle on the pin clk is between 45 % and 55 %, for all the available clock dividers. 8.9.4 i/o circuitry the three data lines i/o, aux1 and aux2 are identical. i/o is referenced to v cc . to enter in the idle state, the i/o line is pulled high via a 10 k ? resistor (i/o to v cc ). the active pull-up feature ensures fast low to high transitions. at the end of the active pull-up pulse, the output voltage depends on the internal pull-up resistor and the load current. the maximum frequency on these lines is 1.5 mhz. 8.9.5 vcc regulator vcc regulator delivers up to 60 ma for class a cards (0 v to 5 v). it also delivers up to 55 ma for class b cards (0 v to 3 v) and up to 35 ma for cla ss c cards (from 0 v to 1.8 v). the vcc has an internal overload detection at approximately 110 ma for class a and b, and 90 ma for class c. this detection is internally f iltered, allowing the card to draw spurious current pulses as defined in emvco specification, without ca using a deactivation. the average current value must remain below the maximum. PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 23 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.9.6 activation sequence the presence of a contact card is indicated to pn7462 through presn signal. if all supply conditions are met, the pn7462 may start an activation sequence. figure 9 shows the activation sequence. the sequencer clock is based on the crystal oscillator: f seq = f xtal /10. when the contact interface is active, the period fo r activation phases is: t = 64/f seq = 23.6 ? s. once the activation sequence is trig gered, the following sequence takes place: ? contact ldos and dc-to-dc converter (when relevant) starts at t 1 ? vcc starts rising from 0 to the required voltage (5 v, 3 v, and 1.8 v) at t 2 ? io rises to vcc at t 3 ? clk starts at t 4 ? rst pin is enabled at t 5 8.9.7 deactivation sequence when triggered by the pn7462, the deact ivation following sequence takes place: ? card reset (pin rst) status goes low ? clock (clk) stopped at low level ? pin io falls to 0 v ? vcc falls to 0 v fig 9. contact interface - activation sequence d d d w 5 6 7 & / . , 2 9 & & 9 8 3 6 w d u w 7 w w w w w PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 24 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller the deactivation sequence is performed in the following cases: ? removal of card; generated automatically by the pn7462 ? overcurrent detection on pin vcc; ge nerated automatically by the pn7462 ? overcurrent detection on pin io; generated automatically by the pn7462 ? detection for overheating; generated automatically by the pn7462 ? pin vbusp going below relevant voltage threshold (optional); part of the pin vbusp monitor ? reset request through software 8.9.8 i/o auxiliary - connecting tda slot extender to address applications where multiple iso/ie c 7816 interfaces are needed, the pn7462 integrates the possibility to connect contact slot extender s like tda8026, tda8020 or tda8035. the following pins are available: ? int_aux ? clk_aux ? io_aux for more details about the connection, re fer to the slot extender documentation. fig 10. deactivation sequence for contact interface d d d w ' & w r ' & f r q y h u w h u / ' 2 v 9 & & , 2 & / . 5 6 7 6 w d u w 7 w w w w PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 25 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.10 contactless interface - 13.56 mhz the pn7462 embeds a high power 13.56 mhz rf frontend. the rf interface implements the rf functionality like antenna driving, th e receiver circuitry, and all the low-level functionalities. it helps to realize an nfc forum or an emvco compliant reader. the pn7462 allows different voltages for the rf drivers. for information related to the rf interface supply, refer section 8.15 . the pn7462 uses an external oscillator, at 27 .12 mhz. it is a clock source for generating rf field and its internal operation. key features of the rf interface are: ? iso/iec 14443 type a & b compliant ? mifare functionality, including mifare classic encryption in read/write mode ? iso/iec 15693 compliant ? nfc forum - nfcip-1 & nfc ip2 compliant ? p2p, active and passive mode ? reading of nfc forum tag types 1, 2, 3, 4, and 5 ? felica ? iso/iec 18000-3 mode 3 ? emvco contactless 2.3.1 and 2.5 1 ? rf level can be achieved without the need of booster circuitry (for some antenna topologies the emv rf-level compliance might physically not be achievable) ? card mode - enabling the emulation of an iso/iec 14443 type a card ? supports passive load modulation (plm) and active load modulation (alm) ? low power card detection (lpcd) ? adjustable rx-voltage level a minimum voltage of 2.3 v helps to use card emulation, and p2p passive target functionality in passive load modulation. a voltage above 2.7 v enables all contactless functionalities. 8.10.1 rf functionality 8.10.1.1 iso/iec14443 a/mifare functionality the physical level of the communication is shown in figure 11 . 1. emvco contactless 2.5 compliance pending PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 26 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller the physical parameters are described in ta b l e 9 . figure 12 shows the data coding and framing according to iso/iec 14443 a/mifare. the internal crc coprocessor calculates the crc value based on the selected protocol. in card mode for higher baudrates, the pari ty is automatically inverted as end of communication indicator. (1) reader to card: 100 % ask; modified miller coded; transfer speed 106 kbit/s to 848 kbit/s (2) card to reader: subcarrier load modulation manchester coded or bpsk, transfer speed 106 kbit/s to 848 kbit/s fig 11. iso/iec 14443 a/mifare read/w rite mode communication diagram d d p , 6 2 , ( & $ & $ 5 ' , 6 2 , ( & $ 5 ( $ ' ( 5 table 9. communication overview for is o/iec 14443 a/mifare reader/writer communication direction signal type transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s reader to card (send data from the pn7462 to a card) f c = 13.56 mhz reader side modulation 100 % ask 100 % ask 100 % ask 100 % ask bit encoding modified miller encoding modified miller encoding modified miller encoding modified miller encoding bit rate (kbit/s) f c / 128 f c / 64 f c / 32 f c / 16 card to reader (pn7462 receives data from a card) card side modulation sub carrier load modulation sub carrier load modulation sub carrier load modulation sub carrier load modulation subcarrier frequency f c / 16 f c / 16 f c / 16 f c / 16 bit encoding manchester encoding bpsk bpsk bpsk fig 12. data coding and framing according to iso/iec 14443 a card response d d n , 6 2 , ( & $ i u d p l q j d w n % g e l w g d w d e l w g d w d e l w g d w d r g g s d u l w \ r g g s d u l w \ v w d u w r g g s d u l w \ v w d u w e l w l v , 6 2 , ( & $ i u d p l q j d w n % g n % g d q g n % g e l w g d w d e l w g d w d e l w g d w d r g g s d u l w \ r g g s d u l w \ v w d u w h y h q s d u l w \ v w d u w e l w l v e x u v w r i v x e f d u u l h u f o r f n v h y h q s d u l w \ d w w k h h q g r i w k h i u d p h PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 27 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.10.1.2 iso/iec14443 b functionality the physical level of the communication is shown in figure 13 . the physical parameters are described in ta b l e 1 0 . 8.10.1.3 felica functionality the felica mode is a ge neral reader/write r to card communication scheme, according to the felica specification. the communication on a physical level is shown in figure 14 . the physical parameters are described in ta b l e 11 . (1) reader to card: nrz; transfer speed 106 kbit/s to 848 kbit/s (2) card to reader: subcarrier load modulation manchester coded or bpsk, transfer speed 106 kbit/s to 848 kbit/s fig 13. iso/iec 14443 b read/write mode communication diagram d d o , 6 2 , ( & % & $ 5 ' , 6 2 , ( & % 5 ( $ ' ( 5 table 10. communication overview fo r iso/iec 14443 b reader/writer communication direction signal type transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s reader to card (send data from the pn7462 to a card) f c = 13.56 mhz reader side modulation 10 % ask 10 % ask 10 % ask 10 % ask bit encoding nrz nrz nrz nrz bit rate [kbit/s] 128/f c 64/f c 32/f c 16/f c card to reader (pn7462 receives data from a card) card side modulation sub carrier load modulation sub carrier load modulation sub carrier load modulation sub carrier load modulation sub carrier frequency f c / 16 f c / 16 f c / 16 f c / 16 bit encoding bpsk bpsk bpsk bpsk fig 14. felica read/write communication diagram d d p ) h o l & d 5 ( $ ' ( 5 3 & ' ) h o l & d & $ 5 ' 3 , & & 3 & ' w r 3 , & & $ 6 . 0 d q f k h v w h u & r g h g e d x g u d w h w r n e d x g 3 , & & w r 3 & ' ! / r d g p r g x o d w l r q 0 d q f k h v w h u & r g h g e d x g u d w h w r n e d x g PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 28 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller note : the pn7462 does not manage felica security aspects. pn7462 supports felica mult iple reception cycles. 8.10.1.4 iso/iec 15693 functionality the physical level of the communication is shown in figure 16 . the physical parameters are described in ta b l e 1 2 . table 11. communication overview for felica reader/writer communication direction signal type transfer speed felica felica higher transfer speeds 212 kbit/s 424 kbit/s reader to card (send data from the pn7462 to a card) f c = 13.56 mhz reader side modulation 8 % to 30 % ask 8 % to 30 % ask bit encoding manchester encoding manchester encoding bit rate f c / 64 f c / 32 card to reader (pn7462 receives data from a card) card side modulation load modulation load modulation bit encoding manchester encoding manchester encoding fig 15. multiple reception cycles - data format d d d / h q 6 w d w x v / h q ( u u r u & r o o ( u u r u 3 u r w ( u u r u ' d w d ( u u r u & o ( u u r u 3 d \ / r d g 6 w d w x v e \ w h ; ; ; 5 ) 8 > @ 5 ) 8 > @ / h q > @ 5 ) 8 > @ 5 ) 8 > @ e \ w h (1) reader to card: 1/256 and 1/4 encoding (2) card to reader: manchester coding fig 16. iso/iec 15693 read/write mode communication diagram d d d , 6 2 , ( & & $ 5 ' , 6 2 , ( & 5 ( $ ' ( 5 table 12. communication overview for iso/ iec 15693 reader/writer reader to label communication direction signal type transfer speed f c / 8192 kbit/s f c / 512 kbit/s reader to label (send data from the pn7462 to a card) reader side modulation 10 % to 30 % ask or 100 % ask 10 % to 30 % ask or 90 % to 100 % ask bit encoding 1/256 1/4 bit length 4.833 ? s 302.08 ? s PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 29 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] fast inventory (page) read command only (icode proprietary command). 8.10.1.5 iso/iec18000-3 mode 3 functionality the iso/iec 18000-3 mode 3 is not described in this document. for a detailed explanation of the protocol, refer to the iso/iec 18000-3 standard. pn7462 supports the following features: ? tari = 9.44 ? s or 18.88 ? s ? downlink: four subcarrier pulse manchester and two subcarrier pulse manchester ? subcarrier: 423 khz (f c / 32) with dr = 0 and 847 khz (f c / 16) with dr = 1 8.10.1.6 nfcip-1 modes the nfcip-1 communication differentiates between an active and a passive communication mode. ? in active communication mode, both initiator and target use their own rf field to transmit data ? in passive communication mode, the target answers to an initiator command in a load modulation scheme. the initiator is active in terms of generating the rf field ? the initiator generates rf field at 13.56 mhz and starts the nfcip-1 communication ? in passive communication mode, the target responds to initiator command in load modulation scheme. in active communicati on mode, it uses a self-generated and self-modulated rf field. table 13. communication overview for iso/ iec 15693 reader/writer label to reader communication direction signal type transfer speed 6.62 kbit/s 13.24 kbit/s [1] 26.48 kbit/s 52.96 kbit/s label to reader (pn7462 receives data from a card) f c = 13.56 mhz card side modulation not supported not supported single (dual) sub carrier load modulation ask single sub carrier load modulation ask bit length ( ? s) - - 37.76 18.88 bit encoding - - manchester coding manchester coding subcarrier frequency (mhz) --f c / 32 f c / 32 fig 17. data coding according to iso/iec 15693 standard mode reader to label d d p s x o v h p r g x o d w h g f d u u l h u a ? v a ? v a p v PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 30 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller pn7462 supports nfcip-1 standard. pn7462 supports active and passive communication mode at transfer speeds of 106 kbit/s, 212 kbit/s, and 424 kbit/s, as defined in the nfcip-1 standard. note : transfer speeds above 424 kbit/s are not defined in the nfcip-1 standard. fig 18. active communication mode table 14. communication overview for active communication mode communication direction transfer speed 106 kbit/s 212 kbit/s 424 kbit/s initiator to target according to iso/iec 14443 a 100 % ask, modified miller coded according to felica, 8-30 % ask manchester coded according to felica, 8-30 % ask manchester coded target to initiator fig 19. passive communication mode k r v w 1 ) & , 1 , 7 , $ 7 2 5 s r z h u h g w r j h q h u d w h 5 ) i l h o g l q l w l d w r u v w d u w v f r p p x q l f d w l r q d w v h o h f w h g w u d q v i h u v s h h g , q l w l d o f r p p d q g u h v s r q v h w d u j h w d q v z h u v d w w k h v d p h w u d q v i h u v s h h g k r v w 1 ) & , 1 , 7 , $ 7 2 5 s r z h u h g i r u g l j l w d o s u r f h v v l q j k r v w k r v w 1 ) & 7 $ 5 * ( 7 1 ) & 7 $ 5 * ( 7 s r z h u h g i r u g l j l w d o s u r f h v v l q j s r z h u h g w r j h q h u d w h 5 ) i l h o g d d q k r v w 1 ) & , 1 , 7 , $ 7 2 5 s r z h u h g w r j h q h u d w h 5 ) i l h o g l q l w l d w r u v w d u w v f r p p x q l f d w l r q d w v h o h f w h g w u d q v i h u v s h h g w d u j h w v d q v z h u v x v l q j o r d g p r g x o d w h g g d w d d w w k h v d p h w u d q v i h u v s h h g k r v w 1 ) & 7 $ 5 * ( 7 s r z h u h g i r u g l j l w d o s u r f h v v l q j d d q PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 31 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller the nfcip-1 protocol is managed in the pn7462 customer application firmware. note : transfer speeds above 424 kbit/s are not defined in the nfcip-1 standard. iso/iec14443 a card operation mode: pn7462 can be addressed as a iso/iec 14443 a card. it means that pn7462 can generate an answer in a load modulation scheme according to the iso/iec 14443 a interface description. note : pn7462 component does not support a complete card protocol. the pn7462 customer application firmware handles it. the following table describes the physical layer of a iso/iec14443 a card mode: nfcip-1 framing and coding: the nfcip-1 framing and coding in active and passive communication mode is defined in the nfcip-1 standard. pn7462 supports the following data rates: nfcip-1 protocol support: the nfcip-1 protocol is not el aborated in this document. the pn7462 component does not implement any of the high-level protocol functions. these high-level protocol func tions are implemented in the microcontroller. for detailed explanation of the protocol, refer to the nfci p-1 standard. however, the datalink layer is according to the following policy: ? speed shall not be changed while there is continuous data exchange in a transaction. table 15. communication overview for passive communication mode communication direction transfer speed 106 kbit/s 212 kbit/s 424 kbit/s initiator to target according to iso/iec 14443 a 100 % ask, modified miller coded according to felica, 8-30 % ask manchester coded according to felica, 8-30 % ask manchester coded target to initiator according to iso/iec 14443 a @106 kb modified miller coded according to felica, > 12 % ask manchester coded according to felica, > 12 % ask manchester coded table 16. iso/iec14443 a card operation mode communication direction iso/iec 14443 a (transfer speed: 106 kbit per second) reader/writer to pn7462 modulation on reader side 100 % ask bit coding modified miller bit length 128/f c pn7462 to reader/writer modulation on pn7462 side sub carrier load modulation subcarrier frequency f c / 16 bit coding manchester coding table 17. framing and coding overview transfer speed framing and coding 106 kbit/s according to the iso/iec 14443 a/mifare scheme 212 kbit/s according to the felica scheme 424 kbit/s according to the felica scheme PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 32 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? transaction includes initializ ation, anticollision methods, and data exchange (in a continuous way means no interruption by another transaction). in order not to disturb current infrastructure based on 13.56 mhz, the following general rules to start nfcip-1 communication are defined: 1. by default, nfcip-1 device is in target mode . it means that its rf field is switched off. 2. the rf level detector is active. 3. only if the application re quires, the nfcip-1 device s witches to initiator mode. 4. an initiator shall only switch on its rf fi eld if the rf level detector does not detect external rf field during a time of t idt . 5. the initiator performs initialization a ccording to the selected mode. 8.10.2 low-power card detection (lpcd) the low-power card detection is an energy saving feature of the pn7462. it detects the presence of a card without starting a communication. communication requires more energy to power the card and takes time, increasing the energy consumption. it is based on antenna detuning detection. wh en a card comes close to the reader, it affects the antenna tuning, wh ich is detected by pn7462. the sensitivity can be varied for adjusting to various environment and applications constraints. remark: reader antenna detuning may have multiple sources such as cards and metal near the antenna. hence it is important to adj ust the sensitivity with care to optimize the detection and power consumption. as the g enerated field is limited, distance for card detection might be reduced compared to normal reader operation. performances depend on the antenna and the sensitivity used. 8.10.3 active load modulation (alm) when pn7462 is used in card emulation mode or p2p passive target mode, it modulates the field emitted by the external reader or nfc passive initiator. to modulate the field, pn 7462 has two possibilities: ? passive load modulation (plm): the pn7462 modifies the antenna characteristics, which is detected by the read er through antenna coupling. (1) type a reader or nfc passive initiator generate the rf and sends commands (2) pn7462 modulates the field of reader for sending its answer fig 20. communication in card emulation of nfc passive target d d d 3 1 $ 8 & $ 5 ' 7 < 3 ( $ ( 0 8 / $ 7 , 2 1 2 5 3 3 3 $ 6 6 , 9 ( 7 $ 5 * ( 7 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 33 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? active load modulation (alm): the pn 7462 generates a small field, in phase opposition with the field emitted by the reader. this modulation is detected by the reader reception stage. the modulation type to use depends on the external reader and the antenna of pn7462 and the application. 8.10.4 contactless interface 8.10.4.1 transmitter (tx) the transmitter is able to drive an antenna circuit connected to outputs tx1 and tx2 with a 13.56 mhz carrier signal. the signal deliver ed on pins tx1 and pin tx2 is a 13.56 mhz carrier, modulated by an envelope signal for energy and data transmission. it can be used to drive an antenna directly, using a few passi ve components for matching and filtering. for a differential antenna configuration, either tx1 or tx2 can be configured to put out an inverted clock. 100 % modulation and severa l levels of amplitude modulation on the carrier can be performed to support 13.56 mhz carrier-based rf-reader/writer protocols. the standards iso/iec14443 a and b, felica and iso/iec18 092 define the protocols. pn7462 transmitter facilitates 10 % and 100 % amplitude m odulation, as per the rf standards supported. the pn7462 embeds an overshoot and undersho ot protection. it is used to configure additional signals on the transmitter output, for controlling the signal shape at the antenna output. 8.10.4.2 receiver (rx) in reader mode, the response of the picc device is coupled from the pcb antenna to the differential input rxp/rxn. the reader mode receiver extracts this signal by first removing the carrier in passive mixers (direct conversion for i and q). it then filters and amplifies the baseband signal before converting to digital values. the conversion to digital values is done with two separate adcs, for i and q channels. both i and q channels have a differential structure, whic h improves the signal quality. the i/q mixer mixes the differential input rf-s ignal down to the baseband. the mixer has a bandwidth of 2 mhz. fig 21. pn7462 output driver d d d 3 5 ( ' 5 , 9 ( 5 6 7 9 ' ' 7 9 ' ' 7 ; 0 0 h q y h o r s h f o n b k l j k v l g h f o n b o r z v l g h k v b j d w h o v b j d w h ! PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 34 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller the down-mixed differential rx input signals are passed to the bba and a band-pass filter. for considering all the protocols (type a/b, felica), the high-pass cut-off frequency of bba is configured between 45 khz and 250 khz. the configuratio n is done in four different steps. the low-pass cut-off frequency is greater than 2 mhz. the output of band-pass filter is further amp lified with a gain factor which is configurable between 30 db and 60 db. the baseband am plifier (bba)/adc i-ch annel and q-channel can be enabled separately. it is required for adc-based card mode functionality as only the i-channel is used in this case. vmid: a resistive divider between avdd and gnd generates vmid. the resistive divider is connected to the vmid pin. an external bl ocking capacitor of typical value 100 nf is connected. automatic gain control (agc): the ? contactless ? interface ? agc ? is ? used? to ? control ? the ? amplitude ? of ? 13.56? mhz ? sine \wave ? input ? signal ? received. ? the ? signal ? is ? received ? at ? the ? antenna ? connected ? between ? the ? pins ? rxp? and ? rxn. ? a ? comparator ? is ? used ? to ? compare ? the ? peak ? value ? of ? the ? input ? signal ? with ? a ? reference ? voltage. a? voltage ? divider ? circ uit ? is ? used ? to ? generate ? the ? reference ? voltage. ? an ? external ? resistor ? (typically ? 3.3 ? k ? ) ? is ? connected ? to ? the ? rx ? input, ? which ? forms ? a ? voltage ? divider ? with ? an ? on \ chip? variable ? resistor. ? the ? voltage ? divider ? circuit ? so ? formed ? has ? a ? 10\bit? resolution. note: the comparator monitors the rxp signal only. by varying the on-chip resistor, the amplitude of the input signal can be modified. the value of on-chip resistor is increased or decreased, depending on the output of the sampled comparator. the on-chip resistor value is adjusted until the peak of the input signal matches the reference voltage. thus, the agc circuit automatically controls the amplitude of the rx input. the internal amplitude contro lling resistor in the agc ha s a default value of 10 k ? . it means that, when the resistor control bits in agc_value_reg <9:0> are all 0, the resistance is 10 k ? . as the control bits are increased, resistors are switched in parallel to the 10 k ? resistor. it lowers the resu ltant resistance value to 5 k ? (agc_value_reg <9:0>, all bits set to 1). mode detector: the mode detector is a functional bl ock of the pn7462 which senses for an rf field generated by another device. the mode detector facilitates to distinguish between type a and felica target mode. the host responds depending on the recognized protocol generated by an initiator peer device. fig 22. receiver block diagram d d d 5 ; 3 9 0 , ' $ * & % % $ % % $ 0 , ; & / . , & / . 4 & / . 5 ; 1 ' $ 7 $ ' $ 7 $ PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 35 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller note : the pn7462 emulates type a cards and peer-to-peer active target modes according to iso / iec18092. 8.10.5 dynamic power control (dpc) the pn7462 supports the dynamic power control (dpc) feature. the dynamic power controls the rf output cu rrent dependent on the loading condition of the antenna. a lookup table is used to configure the output voltage and to control the transmitter current. in addition to the co ntrol of the transmitter current, wave shaping settings can be controlled as well, depending on the selected protocol and the measured antenna load. 8.11 timers the pn7462 includes two 12-bit general-purpose timers (on lfo clock domain) with match capabilities. it also includes two 32 -bit general-purpose timers (on hfo clock domain) and a watchdog timer (wdt). the timers and wdt can be co nfigured through software vi a a 32-bit apb slave interface. 8.11.1 features of timer 0 and timer 1 ? 12-bit counters ? one match register per timer, no captur e registers and capture trigger pins are needed ? one common output line gathering the four timers (timer 0, timer 1, timer 2, and timer 3) ? interrupts ? timer 0 and timer 1 can be concatenated (multiplied) ? timer 0 and timer 1 have two count modes: single-shot or free-running ? timer 0 and timer 1 time-out interrupts can be individually masked ? timer 0 and timer 1 clock source is lfo clock (lfo/2 = 182.5 khz) remark: the timers are dedicated for rf communication. table 18. timer characteristics name clock source frequency counter length resolution maximum delay chaining timer 0 lfo/2 182.5 khz 12-bit 300 ? s 1.2 s no timer 1 lfo/2 182.5 khz 12-bit 300 ? s 1.2 s yes timer 2 hfo 20 mhz 32-bit 50 ns 214 s no timer 3 hfo 20 mhz 32-bit 50 ns 214 s no watchdog lfo/128 2.85 khz 10-bit 21.5 ms 22 s no PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 36 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.11.2 features of timer 2 and timer 3 ? 32-bit counters ? 1 match register per timer, no capture registers and capture trigger pins are needed ? 1 common output line gathering four timers (timer 0, timer 1, timer 2, and timer 3) ? interrupts ? timer 2 and timer 3 have two count modes: single-shot and free-running ? timer 2 and timer 3 time-out interrupts can be individually masked ? timer 2 and timer 3 clock so urce is the system clock 8.12 system tick timer the pn7462 microcontr oller includes a system tick ti mer (systick) that generates a dedicated systick exception at a fixed time interval (10 ms). 8.13 watchdog timer if the microcontroller enters an erroneous state, the watchdog timer resets the microcontroller. when the watchdog timer is enab led, if the user program fails to ?feed? (reload) the watchdog timer within a predetermined time, it generates a system reset. the watchdog timer can be enabled through software. if there is a watchdog timeout leading to a system reset, the timer is disabled automatically. ? 10-bit counter ? based on a 2.85 khz clock ? triggers an interrupt when a predefined counter value is reached ? connected to the arm subsystem nmi (non-maskable interrupt) ? if the watchdog timer is not periodically loaded, it resets pn7462 8.14 clocks the pn7462 clocks are based on the following clock sources: ? 27.12 mhz external quartz ? 27.12 mhz crystal oscillator ? internal oscillator: 20 mhz high frequency oscillator (hfo) ? internal oscillator: 365 khz low frequency oscillator (lfo) ? internal pll at 48 mh z for the usb interface figure 23 indicates the clocks used by each ip. PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 37 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.14.1 quartz oscillator (27.12 mhz) the 27.12 mhz quar tz oscillator is used as a refe rence for all operations where the stability of the clock frequency is important for reliability. it includes contactless interface, contact interface, spi and i 2 c master interfaces, usb pll for the usb interface, and hsuart. regular and low-power crystals can be used. figure 24 shows the circuit for generating stable clock frequency. the quartz and trimming capacitors are off-chip. ta b l e 1 9 describes the levels of accuracy and stability required on the crystal. fig 23. clocks and ip overview d d d 3 / / , 3 % 8 ) ) ( 5 f o l i b s o o b l q b v h o s o o b f o n l q x v e b s o o b f o n l q f o n b x v e b 0 + ] g n b l q s x w b e x i i h u f o n b [ w d o w l h c w l h c ; 7 $ / & / , ) 3 / / & / , ) b ' , * ; 7 $ / 3 / / b , 1 3 8 7 b % 8 ) ) ( 5 b % < 3 $ 6 6 ; 7 $ / b 6 ( / b ( ; 7 ( 5 1 $ / b & / 2 & . & / , ) b 3 / / b 5 ( ) b & / . b 6 ( / ( & 7 > @ s o o b e \ s d v v s o o b f o n r x w s o o b f o n r x w s o o b f o n r x w s o o b f o n l q f o n b [ w d o & / , ) b 3 / / b & / 2 & . b 6 ( / ( & 7 > @ x v e b s o o b l q b v h o w l h c w l h c f o n b [ w d o f o n b l q s x w b e x i i h u 8 6 % b 3 / / b 5 ( ) b & / . b 6 ( / ( & 7 > @ 8 6 % b 3 / / b & / . 2 8 7 b 6 ( / ( & 7 > @ ; 7 $ / 8 6 % 3 / / x v e b s o o b f o n l q f o n b s o o b p f o n b l s b p 3 & 5 b & / . b & ) * ( ; 7 b & / . b 6 ( / & / , ) b $ 1 $ 3 & 5 f o n b s o o b p w l h c w l h c x v e b s o o b f o n r x w b g l y x v e b s o o b f o n r x w fig 24. crystal oscillator connection d d d ; 7 $ / ; 7 $ / & f u \ v w d o 0 + ] & 3 1 $ 8 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 38 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] this requirement is according to fcc r egulations requirements. the frequency should be +/ ? 14 khz to meet iso/iec 14443 and iso/iec 18092. 8.14.2 usb pll the pn7462 integrates a dedicated pll to ge nerate a low-noise 48 mhz clock, by using the 27.12 mhz from the external crystal. the 48 mhz clock generated is used as the usb main clock. following are the usb pll features: ? low-skew, peak-to-peak cycle-to- cycle jitter, 48 mhz output clock ? low power in active mode, low power-down current ? on-chip loop filter, external rc components not needed 8.14.3 high frequency oscillator (hfo) the pn7462 has an internal lo w-power high frequency oscilla tor (hfo) that generates a 20 mhz clock. the hfo is used to generate the system clock. the system clock default value is 20 mhz, and it can be configured to 10 mhz and 5 mhz for reducing power consumption. 8.14.4 low frequency oscillator (lfo) the pn7462 has an internal low-power low frequency oscillator (l fo) that generates a 365 khz clock. the lfo is used by eeprom, por sequencer, contactless interface, timers, and watchdog. 8.14.5 clock configuration and clock gating in order to reduce the overa ll power consumption, the pn7462 facilitates adjustment of system clock. it integrates clock gating mechanisms. the system clock can be configured to the following values: 20 mhz, 10 mhz, and 5 mhz. the clock of the following blocks can be ac tivated or deactivated, depending on the peripherals used: ? contactless interface ? contact interface ? host interfaces ? i 2 c master interface ? spi master interface ? crc engine table 19. crystal requirements symbol parameter conditions min typ max unit f xtal crystal frequency iso/iec and fcc compliancy 27.12 mhz ? f xtal crystal frequency accuracy [1] ? 50 +50 ppm esr equivalent series resistance 50 100 ? c l load capacitance 10 pf p drive drive power 100 ? w PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 39 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? timers ? random generator ? system clock ? eeprom ? flash memory 8.15 power management 8.15.1 power supply sources the pn7462 is powered using the following supply inputs: ? vbus: main supply voltage for internal analog modules, digital logic and memories ? vbusp: supply voltage for the contact interface ? tvdd_in: supply for the contactless interface ? pvdd_in: pad voltage reference and supply of the host interface (hsu, usb, i 2 c, and spi) and the gpios ? pvdd_m_in: pad voltage reference and supply for the master interface (spi and i 2 c) ? dvdd: supply for the internal digital blocks 8.15.2 pn7462 power management unit (pmu) the integrated power management unit (pmu) provides supply for internal analog modules, internal digital logic and memories, pads. it also provides supply voltages for the contactless and contact interface. it automatically adjusts internal regulators to minimize power consumption during all possible power states. the power management unit embeds a mechani sm to prevent the ic from overheat, overconsumption, or overloading the dc-to-dc converter: ? txldo 5 v monitoring ? vcc current limiter ? dc-to-dc converter current overload ? scvdd current overload ? temperature sensor PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 40 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller pn7462 embeds five low drop-o ut regulators (ldo) for en suring the stability of power supply, while the application is running. ? mldo (main ldo): it provides1.8 v supply fo r internal analog, digital and memory modules ? txldo: this ldo can be used to supply the rf transmitter ? pvdd_ldo: pvdd_ldo provides 3.3 v that can be used for all pads supply ? scldo: this ldo provides a 2.4 v output to be used for contact card supply. the main aim is to be able to address class b operation when the voltage available is below 3.9 v. it is achieved by providing a stable input voltage to the internal dc-to-dc converter. ? vcc_ldo: the vcc_ldo pr ovides the supply for the contact smart card some are used while some are optional, like the tx_ldo which is proposed for the rf interface. it is up to the application desi gner to decide whether ldos should be used. 8.15.2.1 main ldo the main ldo (mldo) provides a 1.8 v supp ly for all internal, digital and memory modules. it takes input from vbus. mldo incl udes a current limiter that avoids damage to the output transistors. output supply is available on vdd pin which must be connected externally to the dvdd pin. following are the main ldo features: ? main low-drop-out (mldo) voltage regulator powered by vbus (external supply) fig 25. pn7462 ldos and power pins overview d d d 5 ) w u d q v p l w w h u 7 9 ' ' b 2 8 7 9 8 3 b 7 ; 9 % 8 6 9 % 8 6 3 7 9 ' ' b , 1 p d v w h u l q w h u i d f h s d g v l q w h u q d o d q d o r j e o r f n v ' l j l w d o o r j l f d q g p h p r u l h v p d q g d w r u \ r s w l r q d o 3 9 ' ' b 0 b , 1 s d g v x s s o \ 3 9 ' ' b , 1 3 9 ' ' b 2 8 7 9 ' ' 0 , / ' 2 3 9 ' ' b / ' 2 6 & b / ' 2 9 & & b / ' 2 7 ; b / ' 2 ' 9 ' ' 9 & & 9 8 3 ' & w r ' & f r q y h u w h u PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 41 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? current limiter to avoid damaging the output transistors 8.15.2.2 pvdd_ldo the pvdd_ldo provides 3.3 v supply, that can be used for all digital pads. it may also be used to provide 3.3 v power to external comp onents, avoiding an external ldo. it is supplied by vbus, and requires a minimum voltage of 4 v to be functional. it delivers a maximum of 30 ma. the output pin for pvdd_ldo is pvdd_out. pvdd_ldo is used to provide the necessary supply to pvdd_in and pvdd_m_in (pad supply for master interfaces). when an external supply is used, pvdd_ou t must be connected to the ground. when the ldo output is connected to the ground, the pn7462 chip switches off the pvdd_ldo. the pvdd ldo has a low-power mode, which is used automatically by the pn7462 when the chip is in standby mode or suspend mode. it facilitates supply to host pads and gpios, and to detect wake-up signal s coming from these interfaces. following are the pvdd_ldo features: ? low-drop-out voltage regulator powered by v ddp(vbus) (external supply) ? supports soft-start mode to limit inrush current during the initial charge of the external capacitance when the ldo is powered up ? current limiter to avoid damaging the output transistors note : when pvdd_ldo is used, there must not be any load current drawn from pvdd_ldo during the soft start of the pvdd_ldo. 8.15.2.3 contact interface - scldo ldo the scldo provides a regulated voltage to the dc-to-dc converter, to enable class b operation when v ddp(vbus) is in between 2.7 v to 3.9 v. following are the contact interface features: ? current limiter for short circuit protection ? supports soft-start mode to limit the inrush current during the initial charge of the external capacitance when the ldo is powered up 8.15.2.4 contact interface dc-to-dc converter the pn7462 includes a dc-to-dc converter th at supports class a and class b cards, when the input voltage v ddp(vbusp) is not sufficient. the dc-to-dc converter is a capacitance voltage doubler. it takes power from the scldo. the dc-to-dc converter can be bypassed . its output (vup) is regulated between 3.3 v to 5.5 v. the dc-to-dc converter can work in the following modes: ? follower mode: this mo de is used when v ddp(vbusp) is high enough to provide the desired power to the vcc ldo PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 42 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? doubler mode: this mode is used when v ddp(vbusp) is not high enough to supply the requested v cc output the doubler mode is used in the following conditions: ? class a cards support ? class b cards supp ort, when v ddp(vbusp) is less than 3.9 v for class c cards, the dc-to-dc converter is always in a follower mode. an external capacitor (470 nf) should be connected between sam and sap pins, to ensure the functioning of the dc-to-dc converter. 8.15.2.5 vcc ldo the vcc ldo supplies contact interface supply v cc . following are the vcc ldo features: ? low drop-out voltage regulator ? current limiter for chip and card protection ? automatic deactivation in case of overload 8.15.2.6 txldo the pn7462 consists of an internal transmit ter supply ldo. the txldo can be used to maintain a constant output voltage for the rf interface. the tx ldo is designed to protect the chip from voltage ripple introduced by the power supply on the pin vup_tx. it is powered through the pin vup_tx. the programmable output voltages are: 3.0 v, 3.3 v, 3.6 v, 4.5 v, and 4.75 v. for a given output voltage, vup_tx shall always be higher than 0.3 v. in other words, to supply a 3 v output, the minimum voltage to be applied on vup_tx is 3.3 v. if the voltage is not sufficient, then the voltage at the pin tvdd_out follows the voltage at the pin vup_tx, lowered of 0.3 v. when it is not used, tvdd_out shall be connected to tvdd_in, and tx_ldo shall be turned off. following are the txldo features: ? low-drop-out (txldo ) voltage regulator ? current load up to 180 ma table 20. scldo and dc-to-dc converter modes supported card v ddp(vbusp) sclco mode dc-to-dc converter mode class a > 3 v follower mode doubler mode class b 2.7 v < v ddp(vbusp) < 3.9 v ldo mode doubler mode class b > 3.9 v follower mode follower mode class c > 2.7 v follower mode follower mode PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 43 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? supports soft-start mode to limit inrush current during the initial charge of the external capacitance ? current limiter to avoid damaging the output transistors 8.15.3 power modes the pn7462 offers four different power modes, that enable the user to optimize its energy consumption. they are: ? hard power-down mode ? standby mode ? usb suspend mode ? active mode 8.15.3.1 active mode in active mode, all functionalities are availabl e and all ips can be accessed. it is possible to configure the various clocks (ip clock, system clock) using register settings so that chip consumption is reduced. if ips are not used, they can be disabled. 8.15.3.2 standby mode in standby mode, only a reduced part of the di gital and the analog is active. it reduces the chip power consumption. the possible wake-up sources are still powered. the lfo clock is used to lower the energy needs. active part in standby mode : main ldo is active, in a low-power mode, plus all configured wake -up sources. depending on the application requirements, it is possible to configure pvddl_ldo in active mode, low-power mode or shut down mode when pn7462 is going to standby mode. pvdd_ldo is active in a low-power mode by default. entering in standby mode : the application code triggers standby mode. before entering in standby mode, the pn7462 manages the deactivation of the contact card. the pn7462 has two internal temperature sens ors. if these sensors detect an overheat, the pn7462 is put into standby mode by the application firmware. the chip leaves the standby mode when both temperature sensors indicate that the temperature has come below the configured limit. limitations : standby mode is not possible in the following cases: ? a host communication is in progress ? a wake-up condition is fulfille d. for example, external rf field presence is a wake-up source, and pn7462 detects a field ? the rf field detector is a possible wake-up source, and the rf field detector is disabled ? pvdd is not present 8.15.3.3 suspend mode in suspend mode, clock sources are stopped except lfo. it reduces the chip power consumption. PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 44 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller entering in suspend mode : an interrupt indicates to th e application firmware when no activity has been detected on the usb port for more that 3 ms. the application code triggers the suspend mode. before entering in suspend mode, the pn74 62 manages automatically, the deactivation of the contact card. limitations : suspend mode is prevented in the following cases: ? a host communication is in progress ? a wake-up condition is fulfille d. for example, external rf field presence is a wake-up source, and pn7462 detects a field ? the rf field detector is a possible wake-up source, and the rf field detector is disabled ? no voltage at pin pvdd 8.15.3.4 wake-up from standby mode and suspend mode pn7462 can be woken-up from standby mode, and suspend mode, using the following means: ? host interface: spi, hsuart, i 2 c, and usb if already selected before standby mode (spi, hsuart, and i 2 c) or suspend mode (usb). ? rf field detection (presence of a reader or an nfc device in reader mode or p2p initiator) ? gpio ? contact card insertion, contact card removal ? interrupt generated on the auxiliary uart interface, throu gh the interrupt pin ? wake-up counter, for example to timely check for the presence of any contact or contactless card ? current overconsumption on the pvdd_out, voltage above 5 v on tvdd_in ? temperature sensor: when the pn7462 go es in to standby mode because of over-heating, and when the temperature goes below the sensor configured value, pn7462 wakes-up automatically. each temperature sensor can be configured separately. it is possible to configure the sources as enabled or disabled. 8.15.3.5 hard power-down (hpd) mode the pn7462 hard power-down (hpd), reduces the chip power consumption, by powering down most of the chip blocks. all clocks and ldos are turned off, except the main ldo which is set in low-power mode. entering in hpd mode : if the rst_n pin is set to low, the pn7462 enters in to hard power down (hpd) mode. it also enters in to hpd mode if the v ddp(vbus) goes below the critical voltage necessary for the chip to work (2.3 v) and the auto hpd feature is enabled. exiting the hpd mode : the pn7462 leaves the hpd mode, when both rst_n pin is set to high level and the v ddp(vbus) voltage is above 2.3 v. PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 45 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.15.4 voltage monitoring the voltage monitoring mode detects whether the voltage is within the operational conditions to enable a proper operation of th e rf interface or the contact interface. the following power supplies are monitored: vbus (two voltage monitors), vbus_p (one voltage monitor). section 9.1.2 discusses about the minimum voltages necessary for contactless interface operation and section 9.1.3 for the contact interface operation. [1] n.a. means not applicable. 8.15.4.1 vbus monitor the pn7462 includes up to two levels (2.3 v or 2.7 v) for monitoring the voltage on the vbus pin. if this voltage falls below one of the selected levels , the bod asserts an interrupt signal to the pcr. this signal may be enabled for interrupt in the interrupt enable register in the pcr, to cause a cpu interr upt. alternatively, software can monitor the signal by reading a dedicated stat us register. two threshold levels (2.3 v or 2.7 v) can be selected to cause a forced ha rd power-down (hpd) of chip. 8.15.4.2 vbusp monitor the pn7462 includes three levels (2.7 v, 3. 0 v, and 3.9 v) for monitoring the voltage on the vbusp pin. when the voltage falls below the selected thre shold value, and ct automatic deactivation is enabled in the pcr system register, ha rdware automatically de-activates the ct interface. an interrupt signal is also assert ed to the pcr. this signal can be enabled for interrupt in the interrupt enable register in the pcr, to cause a cpu interrupt. software must check vbusp monitor levels by reading dedicated status registers before starting card activation sequence. 8.15.4.3 pvdd ldo supply monitor the pn7462 includes up to two levels (vbus2: 2.7 v or 4.0 v) for monitoring the voltage on the pvdd ldo input supply. if supply voltage is 4.0 v or above, pvdd ldo can be enabled. the software has to check whether the voltage is sufficient before enabling the ldo. 8.15.5 temperature sensor the pn7462 power management unit provides temperature sensors, associated to the tx_ldo and the contact interface dc-to-dc converter. it detects problems that would result in high power consumption and heating, which could damage the chip and the user device. triggering levels are configurable. following temperatures can be chosen: 135 ? c, 130 ? c, 125 ? c, and 120 ? c. by default, the temperature sensor is set to 120 ? c. table 21. threshold configuration for voltage monitor voltage monitor threshold 1 threshold 2 threshold 3 vbusmon1 2.3 v 2.7 v n.a. [1] vbusmon2 2.7 v 4.0 v n.a. [1] vbusp 2.7 v 3.0 v 3.9 v PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 46 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller when one of the temperature sensors detec ts an increase in temperature above the configured level, an interrupt is generated. the application can then decide to go into standby or suspend mode. the pn registers indicate which temperature sensor generated the interrupt. when the temperature goes below the configured threshold temperature, pn7462 wakes up automatically. 8.16 system control 8.16.1 reset pn7462 has six possible sources for reset. the list of sources is described in table 22 . [1] this feature can be disabled. the watchdog reset, i 2 c reset and soft resets from pcr and arm processor resets the chip except the pcr and the arm debug interface. the power-on reset (por) resets the complete chip including the pcr and arm debug interface. upon reset, the processor executes the first in struction at address 0, which is initially the reset vector mapped from the boot block. at that point, all the processor and peripheral registers are initialized to predetermined values. 8.16.2 brown-out detection (bod) the pn7462 includes up to two levels for monitoring the voltage on the vbus pin. if this voltage falls below one of the selected voltages (2.3 v or 2.7 v), the bod asserts an interrupt signal to the pcr. this signal can be enabled for interrupt in the interrupt enable register in the pcr, to cause a cpu interrup t. alternatively, software can monitor the signal by reading a dedicated status register. two threshold levels (2.3 v and 2.7 v) can be selected to cause a forced ha rd power-down (hpd) of the chip. 8.16.3 apb interface and ahb-lite all apb peripherals are connected to one apb bus. the ahb-lite connects the ahb masters. th e ahb masters include the cpu bus of the arm cortex-m0, host interface, contactless inte rface, spi interface to the flash memory. it also includes eeprom memory, sram, rom, and ahb to apb bridge. 8.16.4 external interrupts pn7462 enables the use of 12 gpios as edge or level sensitive inputs (gpio1 to gpio12). table 22. reset sources source description software - pcr soft reset from the pcr peripheral software - arm software reset form the arm processor i 2 c interface i 2 c standard 3.0 defines a method to reset the chip via an i 2 c command [1] watchdog reset the chip if the watchdog threshold is not periodically reloaded vbus voltage power-on reset sequence; if the voltage is above 2.3 v, reset the chip PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 47 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 8.17 swd debug interface the cortex-m0 processor-based devices use serial wire arm coresight tm debug technology. the pn7462 is configured to support four break points and two watch points. the swd interface can be disabled for having code (or data) read/write access protection. a dedicated swd disable bit is av ailable in the protect ed area of the eeprom memory. once the swd interface is disabled , it is not possible to enable it anymore. 8.17.1 swd interface features ? run control of the processor allowing to start and stop programs ? single step one source or assembler line ? set breakpoints while the processor is running ? read/write memory contents and peripheral registers on-the-fly ? ?printf? like debug messages through the swd interface 9. application design-in information 9.1 power supply connection the following table indicates the power sources for all the pn7462 power inputs. [1] when external supply and pvdd_out are not used, pvd d_out must be connected to the ground, with a ground resistance of less than 10 ? . table 23. power supply connection power inputs power sources comment vbus external source chosen according to the expected performances (contact interface and cla ss a/b/c support, rf power when tx_ldo is used, global power consumption) vbusp external source; connected to vbus vbusp is connected to vbus, with the addition of a decoupling capacitor tvdd_in external supply or using the tx_ldo external supply can be used (up to 5.5 v) to increase rf power pvdd_in external supply or using pvdd_ldo pvdd_ldo can be used, when v ddp(vbus) > 4 v. it makes a regulated 3.3 v supply available to gpio and host interface pads, without the addition of an external ldo for 1.8 v, external supply is used pvdd_m_in external supply or using pvdd_ldo pvdd_ldo can be used, when v ddp(vbus) > 4 v. it makes a regulated 3.3 v supply available to gpio and host interface pads, without the addition of an external ldo external supply is used for 1.8 v dvdd connected to the vdd out put vdd provides 1.8 v stabilized supply, out of the main_ldo PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 48 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 9.1.1 powering up the microcontroller the schematics in figure 26 describe the power supply of the chip (v ddp(vbus) ), including the digital blocks supply (dvdd). it indicates two possibilities to supply the pads, using the internal ldo, or using an external supply. the internal ldo requires that v ddp(vbus) > 4 v. it avoids the requirement of a separate ldo when v ddp(vbus) has a sufficient voltage. power supply is available to pads through pvdd_in (host interface). similarly, power supply is available to mast er interface pads through pvd d_m_in. when pvvd _ldo is used, maximum total current available from pvdd_out for the pads supply is 30 ma. when an external source is used for pv dd_in and pvdd_m_in, pvdd_out must be connected to the ground, with a ground resistance of less than 10 ? . 9.1.2 powering up the contactless interface powering of contactless interface is done though tvdd_in. internal ldo (txldo) or external supply can be used. (1) powering up the microcontroller and the digital blocks (dvdd). (2) two possibilities for powering the pad interfaces (pvdd_in and pvdd_m_in). remark: the capacitance must be chosen so that the capacitance value is correct at 5 v fig 26. powering up the pn7462 microcontroller 9 ' ' ' 9 ' ' ? ) d d d 9 % 8 6 9 ' ' 3 9 % 8 6 , ' ' 3 9 % 8 6 q ) 3 9 ' ' b 2 8 7 3 9 ' ' b , 1 3 9 ' ' b 0 b , 1 ? ) 9 % 8 6 9 ' ' 3 9 % 8 6 , ' ' 3 9 % 8 6 q ) 3 9 ' ' b 2 8 7 3 9 ' ' b , 1 3 9 ' ' b 0 b , 1 9 % 8 6 9 ' ' 3 9 % 8 6 , ' ' 3 9 % 8 6 h [ w h u q d o v x s s o \ q ) ? ) 3 1 $ 8 3 1 $ 8 3 1 $ 8 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 49 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller note: the tvdd_out pin must not be left floating. it should be at the same voltage as the tvdd_in pin. the power design must be designed properly to be able to deliver a clean power supply voltage in any case (external tvdd or internal tx_ldo internal supply), tvdd_in supply must be stable before turning on the rf field. the capacitor shall be 6.8 ? f or higher (upto10 ? f) the capacitance value must be chosen so that the capacitance value is correct at 5 v. (1) using txldo (2) without using txldo fig 27. powering up the contactless interface using a single power supply 7 9 ' ' b 2 8 7 7 9 ' ' b , 1 7 ; 7 ; 7 9 6 6 ? ) d q w h q q d v x s s o \ d d d 7 9 ' ' b 2 8 7 9 8 3 b 7 ; 9 % 8 6 9 8 3 b 7 ; 7 9 ' ' b , 1 7 ; 7 ; 7 9 6 6 ? ) 9 % 8 6 3 1 $ 8 v x s s o \ d q w h q q d v x s s o \ q ) 3 1 $ 8 v x s s o \ q ) 3 1 $ 8 3 1 $ 8 the capacitance value must be chosen so that the capacitance value is correct at 5 v. (1) using txldo. (2) without using txldo. fig 28. powering up the contactless interface using an external rf transmitter supply 3 1 $ 8 5 ) w u d q v p l w w h u v x s s o \ 7 9 ' ' b 2 8 7 9 8 3 b 7 ; 7 9 ' ' b , 1 7 ; 7 ; 7 9 6 6 ? ) 9 % 8 6 3 1 $ 8 v x s s o \ d q w h q q d v x s s o \ q ) ? ) d d d 3 1 $ 8 5 ) w u d q v p l w w h u v x s s o \ 7 9 ' ' b 2 8 7 9 8 3 b 7 ; 7 9 ' ' b , 1 7 ; 7 ; 7 9 6 6 ? ) 9 % 8 6 3 1 $ 8 v x s s o \ d q w h q q d v x s s o \ q ) 3 1 $ 8 3 1 $ 8 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 50 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller every noise level on top of the supply voltage can disturb the rf communication performance of the pn7462. therefore, specia l attention must be pa id to the filtering circuit. when powering up the device through the usb interface, tvdd capacitor shall be such that the maximum capacitance on vbus is as per the usb specification. 9.1.3 powering up the contact interface contact interface is powered through vbusp . vbusp must be conn ected to vbus, as per the schematic in figure 29 . in order to provide the right voltage needed for the various iso/iec 7816 contact card classes (a, b, or c), the following voltages are needed: ? v ddp(vbusp) > 2.7 v: support of class b and class c contact cards ? v ddp(vbusp) > 3 v: support of class a contact cards remark: to support class a cards, dc-to-dc conver ter is used. to support class b cards with v ddp(vbusp) < 3.9 v, dc-to-dc converter is used. figure 30 indicates the method to connect the pi ns related to contact interfaces, when no contact interface is used. (1) the capacitances values must be chosen so th at the capacitance values are correct at 5.6 v. fig 29. powering up the contact interface d d d 6 & 9 ' ' 9 % 8 6 3 9 % 8 6 9 ' ' 3 9 % 8 6 , ' ' 3 9 % 8 6 * ' 1 3 6 $ 0 6 $ 3 9 8 3 9 & & * 1 ' & q ) ? ) q ) q ) q ) q ) ? ) 3 1 $ 8 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 51 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 9.2 connecting the usb interface when the usb interface is not used, the usb_vbus pin shall be connected to the ground. fig 30. contact interface power supply connection when contact interface is not used d d d 6 & 9 ' ' 9 % 8 6 3 ? ) 9 % 8 6 f r q q h f w l r q v z k h q & 7 l q w h u i d f h l v q r w x v h g 9 ' ' 3 9 % 8 6 , ' ' 3 9 % 8 6 q f * ' 1 3 6 $ 0 q f q f q f q f 6 $ 3 9 8 3 9 & & * 1 ' & 3 1 $ 8 (1) c p is optional. fig 31. usb interface on a bus-powered device d d d 3 1 $ 8 & s q ) 8 6 % b 9 % 8 6 8 6 % b ' 3 8 6 % b ' 0 5 v n 8 6 % f r q q h f w r u PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 52 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 9.3 connecting the contact interface the following diagrams indicate the method to connect the contact interface, when the contact interface is used, and when it is not used. (1) to place close to c1 (vcc) pin of the ca rd connector, with good connection to the ground. (2) place close to vcc pin, with good connection to gndc. fig 32. connecting the contact interface fig 33. connection of contact interface when not used d d d 3 1 $ 8 3 5 ( 6 $ 8 ; & / . 5 6 7 * 1 ' & & & & & & & & & 9 3 9 ' ' b , 1 3 5 ( 6 & q ) 5 & q ) 9 & & , 2 $ 8 ; d d d 3 1 $ 8 3 5 ( 6 $ 8 ; & / . 5 6 7 * 1 ' & 9 & & f r q q h f w l r q v z k h q & 7 l q w h u i d f h l v q r w x v h g , 2 $ 8 ; q f q f q f q f q f q f q f PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 53 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 9.4 connecting the rf interface 10. limiting values [1] eia/jesd22-a114-d. fig 34. rf interface - example of connection to an antenna d d d 3 1 $ 8 $ 1 7 5 ; 7 ; 7 9 6 6 7 ; 5 ; $ 1 7 9 0 , ' & & & q ) & d q w & & & d q w & q ) & q ) 5 d q w h q q d d q w h q q d / / 5 & & table 24. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v esd electrostatic discharge voltage human body model (hbm) on card pins io, rst, vcc, aux1, clk, aux2, presn [1] ? 12 +12 kv on all pins except contact interface pins [1] ? 2+2kv charged device model (cdm) on all pins [1] ? 1+1kv t stg storage temperature non-operating ? 55 +150 ?c t j(max) maximum junction temperature - +125 ?c p tot total power dissipation reader mode; v ddp(vbus) = 5.5 v - 1050 mw table 25. limiting values for gpio1 to gpio12 symbol parameter conditions min max unit v i input voltage ? 0.3 4.2 v table 26. limiting values for i 2 c master pins (i2cm_sda, i2cm_scl) symbol parameter conditions min max unit v i input voltage ? 0.3 4.2 v PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 54 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] maximum/minimum voltage above the maximum operating range and be low ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable fail ure. failure includes the loss of reliabi lity and shorter life time of the device. table 27. limiting values for spi master pins ( spim_nss, spim_miso, spim_mosi and spi_clk) symbol parameter conditions min max unit v i input voltage ? 0.3 4.2 v table 28. limiting values for host inte rfaces atx_a, atx_b, atx_c, atx_d in all configurations (usb, hsuart, spi and i 2 c) symbol parameter conditions min max unit v i input voltage ? 0.3 4.2 v table 29. limiting values for crystal oscillator in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v ih high-level input voltage xtal1, xtal2 0 2.2 v table 30. limiting values for power supply in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v ddp(vbus) power supply voltage on pin vbus [1] ? 0.3 6 v v ddp(vbusp) power supply voltage on pin vbusp [1] ? 0.3 6 v pin supply voltage for host interface and gpios (on pin pvdd_in) v dd(pvdd) pvdd supply voltage on pin pvdd_in; power supply for host interfaces and gpios [1] ? 0.3 4.2 v pin supply voltage for master interfaces (on pin pvdd_m_in) v dd(pvdd) pvdd supply voltage on pin pvdd_m_in; power supply for master interfaces [1] ? 0.3 4.2 v rf interface ldo (pin vup_tx) v i(ldo) ldo input voltage for rf interface ldo [1] ? 0.3 6 v rf transmitter (pin tvdd_in) v dd(tvdd) tvdd supply voltage for rf interface transmitter [1] ? 0.3 6 v table 31. limiting values for contact interface in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v ih high-level input voltage on card pins io, rst, aux1, aux2, clk ? 0.3 5.75 v table 32. protection and limita tions for contact interface symbol parameter conditions min typ max unit i olim output current limit on io, c4, c8 class a, b, c 5 8 15 ma i sd shutdown current on pin v cc = 5 v 70 85 110 ma on pin v cc = 3 v (doubler mode) 75 90 110 ma on pin v cc = 3 v (follower mode) 75 90 110 ma on pin v cc = 1.8 v 60 70 90 ma PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 55 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] maximum/minimum voltage above the maximum operating range and be low ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable fail ure. failure includes the loss of reliabi lity and shorter life time of the device. 11. recommended operating conditions 12. thermal characteristics table 33. limiting values for rf interface in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v i input voltage on pins rxn and rxp 0 2.2 v table 34. operating conditions symbol parameter conditions min typ max unit t amb ambient temperature jdec pcb ??? 0.5 ? 40 25 85 ?c v ddp(vbus) power supply voltage on pin vbus external pvdd supply, card emulation and passive target (plm) 2.3 - 5.5 v external pvdd supply, reader mode, nfc initiator and passive/active target mode (alm and plm) 2.7 - 5.5 v internal pvdd_ldo supply, reader mode, nfc initiator and passive/active target mode (alm and plm) 4- 5.5v v ddp(vbusp) power supply voltage on pin vbusp class b and class c contact card 2.7 - 5.5 v class a, class b, and class c contact card 3- 5.5v host interface and gpios pin power supply (pin pvdd_in) v dd(pvdd) pvdd supply voltage for digital pins 1.8 v pin supply 1.65 1.8 1.95 v 3.3 v pin supply 3 3.3 3.6 v spi master and i 2 c master interfaces pin power supply (on pin pvdd_m_in) v dd(pvdd) pvdd supply voltage for master pins 1.8 v pin supply 1.65 1.8 1.95 v 3.3 v pin supply 3 3.3 3.6 v rf interface ldo (pin vup_tx) v i(ldo) ldo input voltage tx_ldo supply for powering up rf interface 355.5v rf interface transmitter i dd(tvdd) tvdd supply current on pin tvdd_in - - 250 ma table 35. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air with exposed pad soldered on a four-layer jedec pcb 40 ?k/w PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 56 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13. characteristics 13.1 static characteristics 13.1.1 gpio static characteristics table 36. static characteri stics for rst_n input pin data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit v ih high-level input voltage 1.1 - v ddp(vbus) v v il low-level input voltage 0 - 0.4 v i ih high-level input current v i = v ddp(vbus) --1 ? a i il low-level input current v i = 0 v ? 1- - ? a c in input capacitance - 5 - pf table 37. static characteristics for irq input pin data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma v pvdd_in ? 0.4 -v pvdd_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 20 pf r pull-down extra pull down extra pull-down is activated in hdp 0.45 - 0.8 m ? table 38. static charac teristics for dwl_req symbol parameter conditions min typ max unit v ih high-level input voltage v pvvd_in = 1.8 v 0.65 ?? v pvvd_in --v v il high-level input voltage v pvvd_in = 1.8 v - - 0.35 ? v pvvd_in v v ih high-level input voltage v pvvd_in = 3.3 v 2 - - v v il high-level input voltage v pvvd_in = 3.3 v - - 0.8 v i ih high-level input current v i = pvdd_in - - 1 ? a i il low-level input current v i = 0 v ? 1- - ? a c l load capacitance - 5 - pf table 39. static characteri stics for gpio1 to gpio21 symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma v pvdd_in ??? 0.4 -v pvdd_in v v ol low-level output voltage i oh < 3 ma 0 - 0.4 v v ih high-level input voltage v pvdd_in = 3.3 v 2 - - v v pvdd_in = 1.8 v 0.65 ?? v pvdd_in --v PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 57 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.1.2 static characteristics for i 2 c master v il low-level input voltage v pvdd_in = 3.3 v - - 0.8 v v pvdd_in = 1.8 v - - 0.35 ?? v pvdd_in v v hys hysteresis voltage v pvdd_in = 1.8 v and v pvdd_in = 3.3 v 0.1 ?? v pvdd_in --v i oz off-state output current v o = 0 v; v o =v pvdd_in ; on-chip pull-up/pull-down resistors disabled - - 1000 na r pd pull-down resistance v pvdd_in = 3.3 v 65 90 120 k ? v pvdd_in = 1.8 v 65 90 120 k ? r pu pull-up resistance v pvdd_in = 3.3 v 65 90 120 k ? v pvdd_in = 1.8 v 65 90 120 k ? i osh short circuit current output high drive high; cell connected to ground; v pvdd_in = 3.3 v --58ma drive low; cell connected to pvdd_in; pvdd_in = 1.8 v --30ma i osl short circuit current output low v oh =v pvdd_in =3.3 v --54ma v oh =v pvdd_in =1.8 v --37ma i il low-level input current v i = 0 v ? 1--a i ih high-level input current v i = v pvdd_in --1 a i oh high-level output current v oh = v pvdd_in --3m a i ol low-level output current v ol = 0 v - - 3 ma table 39. static characteri stics for gpio1 to gpio21 ?continued symbol parameter conditions min typ max unit table 40. static characteristics for i 2 cm_sda, i 2 cm_scl - s symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma 0.7 ? v pvdd_m_in -v pvdd_m_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 10 pf v ih high-level input voltage 0.7 ? v pvdd_m_in --v v il low-level input voltage - - 0.3 ? v pvdd_m_in v i ih high-level input current v i = v pvdd_m_in --1 ? a i il low-level input current v i = 0 v ? 1- - ? a c in input capacitance - 5 - pf PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 58 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.1.3 static characteristics for spi master 13.1.4 static characteristics for host interface table 41. static characteristics for spim_mosi symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma v pvdd_m_in ??? 0.4 - v pvdd_m_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 20 pf table 42. static charac teristics for spim_nss symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma v pvdd_m_in ?? 0.4 - v pvdd_m_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 20 pf table 43. static characteristics for spim_miso symbol parameter conditions min typ max unit v ih high-level input voltage v pvdd_m_in = 1.8 v 0.65 ? v pvdd_m_in -- v v il low-level input voltage v pvdd_m_in = 1.8 v - - 0.35 ?? v pvdd_m_in v v ih high-level input voltage v pvdd_m_in = 3.3 v 2 - - v v il low-level input voltage v pvdd_m_in = 3.3 v - - 0.8 v i ih high-level input current v i = v pvdd_m_in --1 a i il low-level input current v i = 0 v ? 1-- a c in input capacitance - 5 - pf table 44. static charac teristics for spi_sclk symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma v pvdd_m_in ?? 0.4 - v pvdd_m_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 20 pf table 45. static characteristics for atx_ used as spi_nss, atx_ used as i 2 cadr0, atx_ used as spi_sck, atx_ used as spi_mosi symbol parameter conditions min typ max unit v ih high-level input voltage v pvdd_in = 1.8 v 0.65 ? v pvdd_m_in -- v v il low-level input voltage v pvdd_in = 1.8 v - - 0.35 ? v pvdd_m_in v v ih high-level input voltage v pvdd_in = 3.3 v 2 - - v v il low-level input voltage v pvdd_in = 3.3 v - - 0.8 v i ih high-level input current v i = v pvdd_in --1 a i il low-level input current v i = 0 v ? 1-- a c in input capacitance - 5 - pf PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 59 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller table 46. static characteristics of atx_ used as i 2 csda, atx_ used as i 2 cscl symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma 0.7 ? v pvdd_in -v pvdd_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 10 pf v ih high-level input voltage 0.7 ? v pvdd_in -- v v il low-level input voltage - - 0.3 ? v pvdd_in v i ih high-level input current v i = v pvdd_in --1 ? a i il low-level input current v i = 0 v ? 1-- ? a c in input capacitance - 5 - pf table 47. static characteristics of atx_ used as spimiso symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma v pvdd_in ? 0.4 - v pvdd_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 20 pf table 48. usb characteristics data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit i oz off-state output current 0 v < v i < 3.3 v ? 10 - 10 ? a v ddp(vbus) power supply voltage on pin vbus 4-5.5v v di differential input sensitivity voltage (d+) ?? (d ? )0.2-- v v cm differential common mode voltage range includes v di range 0.8 - 2.5 v v th(rs)se single-ended receiver switching threshold voltage 0.8 - 2 v v ol low-level output voltage for low-speed or full-speed; r l of 1.5 k? to 3.6 v --0 . 3v v oh high-level output voltage driven; for low- speed or full-speed; r l of 15 k ? to gnd 2.8 - v pvdd_in v c trans transceiver capacitance pin to gnd - 15 pf z drv driver output impedance for driver which is not high-speed capable with 33 ? series resistor; steady state drive 28 - 44 ? v crs output signal crossover voltage 1.3 - 2 v PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 60 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.1.5 clock static characteristics [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c) with nominal supply voltages. table 49. static characteristic s of hsu_tx and hsu rts pin data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit v oh high-level output voltage i oh < 3 ma v pvdd_in ?? 0.4 - v pvdd_in v v ol low-level output voltage i ol < 3 ma 0 - 0.4 v c l load capacitance - - 20 pf table 50. static characteri stics of hsu_rx, hsu_cts data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit v ih high-level input voltage v pvdd_m_in = 1.8 v 0.65 ? v pvdd_in -- v v il high-level input voltage v pvdd_m_in = 1.8 v - - 0.35 ? v pvdd_in v v ih high-level input voltage v pvdd_m_in = 3.3 v 2 - - v v il high-level input voltage v pvdd_m_in = 3.3 v - - 0.8 v i ih high-level input current - - 1 ? a i il low-level input current ? 1-- ? a c l load capacitance - 5 - pf table 51. static characteristi cs of xtal pin (xtal1, xtal2) t amb = ? 40 ? c to +85 ? c symbol parameter [1] conditions min typ [2] max unit input clock characteristics on xtal1 when using pll v~i(p-p) peak-to-peak input voltage 0.2 - 1.65 v xtal pin characteristics xtal pll input i ih high-level input current v i = v dd --1 ? a i il low-level input current v i = 0 v ? 1 - - ? a v i input voltage - - v dd v v al input voltage amplitude 200 - - mv c in input capacitance all power modes - 2 - pf pin characteristics for 27. 12 mhz crystal oscillator c in input capacitance pin xtal1 - 2 - pf c in input capacitance pin xtal2 - 2 - pf PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 61 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.1.6 static characteristics - power supply table 52. static characteristics for power supply data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit i ddp(vbusp) power supply current on pin vbusp external supply current for contact interface, in operating mode -- 200ma pin supply: pvdd_ldo v o(ldo) ldo output voltage v ddp(vbus) >= 4.0 v, i pvddout <= 30 ma 33.33.6v i dd(pvdd_out) maximum supply current for pin pvdd_out - - 30 ma pin supply for host interface and gpios (on pin pvdd_in) i dd(pvdd) pvdd supply current - - 25 ma pin supply for master interfaces (on pin pvdd_m_in) i dd(pvdd) pvdd supply current - - 25 ma contactless interface: tx_ldo (pins vup_tx, tvdd_out) v i(ldo) ldo input voltage 3 - 5.5 v i l(ldo)(max) maximum ldo load current -- 180ma v o(ldo) ldo output voltage dc output voltage (target: 3.0 v) 5.5 v > v i(ldo) > 3.3 v 2.8 3 3.25 v dc output voltage (target: 3.0 v) 3.3 v > v i(ldo) > 2.7 v -v i(ldo) ? 0.3 -v dc output voltage (target: 3.3 v) 5.5 v > v i(ldo) > 3.6 v 3.1 3.3 3.55 v dc output voltage (target: 3.3 v) 3.6 v > v i(ldo) > 2.7 v -v i(ldo) ? 0.3 -v dc output voltage (target: 3.6 v) 5.5 v > v i(ldo) > 3.9 v 3.4 3.6 3.95 v dc output voltage (target: 3.6 v) 3.9 v > v i(ldo) > 2.7 v -v i(ldo) ? 0.3 -v dc output voltage (target: 4.5 v) 5.5 v > v i(ldo) > 5.0 v 4.34.5 4.9v dc output voltage (target: 4.7 v) 5.5 v > v i(ldo) > 5.0 v 4.55 4.75 5.2 v i o(ldo) ldo output current v i(ldo) = 5.5 v - - 180 ma contactless interface: rf transmitter (on pin tvdd_in) i dd(tvdd) tvdd supply current maximum current supported by the rf transmitter -- 250ma contact interface: smart card power supply (pin vcc) c dec decoupling capacitance connected on pin vcc (220 nf + 220 nf 10 %) 396 570 1000 nf PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 62 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller v cc supply voltage class a; i cc < 60 ma 4.75 5 5.25 v class b; i cc < 50 ma 2.85 3 3.15 v class c; i cc < 30 ma 1.71 1.8 1.89 v class a; current pulses of 40 na with i cc < 200 ma, t w < 400 ns 4.6- 5.4v class b; current pulses of 40 na with i cc < 200 ma, t w < 400 ns 2.76 - 3.24 v class c; current pulses of 12 na with i cc < 200 ma, t w < 400 ns 1.66 - 1.94 v v ripple(p-p) peak-to-peak ripple voltage from 20 khz to 200 mhz - - 350 mv sr slew rate on pin vcc 5 v, class a cards 0.02 - 0.025 v/ ? s 3 v, class b cards 0.012 - 0.015 v/ ? s 1.8 v, class c cards 0.0072 - 0.009 v/ ? s i cc supply current class a - - 60 ma class b - - 55 ma class c - - 35 ma pin vcc shorted to ground - - 110 ma contact interface: dc-to-dc converter v sap sap (dc-to-dc converter) - high-level output voltage v ddp(vbusp) = 5 v, v cc = 5 v; i cc <60ma dc -- 9v v ddp(vbusp) = 5 v, v cc = 3 v; i cc <55ma dc -- 5v v ddp(vbusp) = 5 v, v cc = 1.8 v; i cc <35 ma dc -- 5v v ddp(vbusp) = 3.3 v, v cc = 5 v; i cc <60 ma dc -- 9v v ddp(vbusp) = 3.3 v, v cc = 3 v; i cc <55 ma dc -- 9v v ddp(vbusp) = 3.3 v, v cc = 1.8 v; i cc <35 ma dc -- 3.3v v up v up - high-level output voltage class a; v ddp(vbusp) = 3 v to 5 v, i cc < 60 ma 5.35 - 5.9 v class b; i cc < 55 ma 3.53 - 5.5 v class c, v ddp(vbusp) = 2.7 v to 5.5 v, i cc < 35 ma dc 2.4- 5.5v c sapsam dc-to-dc converter capacitance connected between sap and sam with v ddp(vbusp) = 3 v 300 470 600 nf c vup dc-to-dc converter capacitance connected on pin vup 1.5 2.7 4.7 f voltage detector for the dc-to-dc converter v det detection voltage on pin vbusp for doubler selection, follower/doubler for class b card 3.775 3.9 4.2 v table 52. static characteristics for power supply ?continued data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 63 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller table 53. static characteristics for voltage monitors t amb = ? 40 ? c to +80 ? c symbol parameter conditions min typ max unit v (th)hl negative-going threshold voltage vbus monitor; set to 2.3 v 2.15 2.3 2.45 v set to 2.7 v 2.6 2.75 2.95 v set to 4.0 v 3.6 3.8 3.9 v v hys hysteresis voltage vbus monitor set to 2.3 v 100 150 200 mv set to 2.7 v 100 150 200 mv set to 4.0 v 40 80 100 mv v (th)hl negative-going threshold voltage vbusp monitor set to 2.7 v 2.45 2.56 2.65 v set to 3.0 v 2.68 2.825 2.95 v set to 3.9 v 3.7 3.9 4.1 v v hys hysteresis voltage vbusp monitor set to 2.7 v 12 25 35 mv set to 3.0 v 14 30 40 mv set to 3.9 v 20 35 55 mv PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 64 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.1.7 static characteristics for power modes 13.1.8 static characteristics for contact interface table 54. static characteristics for power modes t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit i ddp(vbus) power supply current on pin vbus active mode; v ddp(vbus) = 5.5 v, external pvdd, external tvdd, all ip clocks disabled code while(1){} executed from flash; -6.5- ma active mode; v ddp(vbus) = 5.5 v, external pvdd, external tvdd, all ip clocks enabled code while(1){} executed from flash; -8.5- ma suspend mode; v ddp(vbus) = 5.5 v, external pvdd, t = 25 ?c - 120 250 ? a v bus = 5.5 v, t = 25 c, internal pvdd ldo, including d+ and d ? pull-up - 360 440 a standby mode; v ddp(vbus) =3.3 v; external pvdd supply; t amb =25 ?c -18- ? a standby mode; v ddp(vbus) =5.5 v; v internal pvdd supply; t amb = 25 ?c -55- ? a hard power down; v ddp(vbus) = 5.5 v; rst_n = 0 v; t amb =25 ?? c -1218 ? a table 55. static characteristics for contact interface t amb = ? 40 ? c to +80 ? c symbol parameter conditions min typ max unit data lines (pins io, aux1, aux2) v o output voltage on pin io inactive mode, no load 0 - 0.1 v inactive mode, i i/o = 1 ma 0 - 0.3 v v ol low-level output voltage pin io configured as output i ol = 1 ma (class a,b), 500 ? a (class c) 0 - 0.15 ? v cc v pin io configure as output, i ol <15ma 0-0.4 v v oh high-level output voltage pi n io configure as output, i oh < ? 200 a, v cc = 5 v, 3 v and 1.8 v; active pull-up 0.9 ? v cc -v cc v pin io configure as output, i oh < ? 20 ? a; v cc = 1.8 v 0.8 ? v cc -v cc v pin io configure as output, i oh <15ma 0-0.4 v v il low-level input voltage pin io configure as input 0 - 0.2 ? v cc v PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 65 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller v ih high-level input voltage 0.6 ? v cc -v cc v v hys hysteresis voltage on pin io 20 75 120 mv i il low-level input current on pin io; v il = 0 v - - 750 ? a i lh high-level leakage current on pin io; v ih =v cc --10 ? a r pu pull-up resistance connected to v cc 7 10 13 k ? reset output to the card v o output voltage inactive mode; no load 0 - 0.1 v inactive mode; i o =1ma 0 - 0.3 v v ol low-level output voltage i ol = 200 a, v cc = 5 v and v cc =3v 0-0.3 v i ol = 200 a, v cc = 1.8 v 0 - 0.1 ? v cc v v oh high-level output voltage i oh = ? 200 ? a0.9 ? v cc -v cc v clock output to the card v o output voltage inactive mode; no load 0 - 0.1 v inactive mode; i o = 1 ma 0 - 0.3 v v ol low-level output voltage i ol = 200 ? a 0 - minimum (0.1 ? v cc ; 0.3) v v oh high-level output voltage i oh = ? 200 ? a0.9 ? v cc -v cc v card presence input v il low-level input voltage ? 0.3 - 0.3 ?? v pvdd_in v v ih high-level input voltage 0.7 ?? v pvdd_in -v pvdd_in + 0.3 v v hys hysteresis voltage 0.03 ?? v pvdd_in -- v i ll low-level leakage current v il = 0 - - 1 ? a i lh high-level leakage current v ih = v pvdd_in --5 ? a table 55. static characteristics for contact interface ?continued t amb = ? 40 ? c to +80 ? c symbol parameter conditions min typ max unit PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 66 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.1.9 static characteristics rf interface 13.2 dynamic characteristics table 56. static characteristics for rf interface data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit pins ant1 and ant2 z impedance between ant1 and ant2; low impedance - 10 17 ? pins rxn and rxp v i(dyn) dynamic input voltage on pins rxn and rxp - - v dd ? 0.05 v c in input pin capacitance on pins rxn and rxp - 12 - pf z impedance between pins rx to vmid; reader, card emulation and p2p modes 0 - 15 k ? v det detection voltage card emulation and target modes; configuration for 19 mv threshold --30mv (p-p) pins tx1 and tx2 v oh high-level output voltage pins tx1 and tx2; t vdd_in = 3.1 v and i oh =30ma v tvdd_in ? 150 -- mv v ol low-level output voltage pins tx1 and tx2; t vdd_in = 3.1; i tx = 30 ma - - 200 mv r ol low-level output resistance v tx = v tvdd ? 100 mv; cwgsn = 01h --80 ? v tx = v tvdd ?? 100 mv; cwgsn = 0fh --10 ? r oh high-level output resistance v tx = v tvdd ?? 100 mv - - 10 ? table 57. dynamic characteristics for irq input pin data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit t f fall time high speed; c l = 12 pf; v pvdd_in = 3.3 v 1 - 3.5 ns high speed; c l = 12 pf; v pvdd_in = 1.8 v 1- 3.5ns t f fall time slow speed; c l = 12 pf; v pvdd_in = 3.3 v 3 - 10 ns slow speed; c l = 12 pf; v pvdd_in = 1.8 v 2 - 10 ns PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 67 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.2.1 flash memory dynamic characteristics 13.2.2 eeprom dynamic characteristics 13.2.3 gpio dynamic characteristics t r rise time high speed: c l = 12 pf; v pvdd_in = 3.3 v 1- 3.5ns high speed: c l = 12 pf; v pvdd_in = 1.8 v 1- 3.5ns t r rise time slow speed: c l = 12 pf; v pvdd_in = 3.3 v 3 - 10 ns slow speed: c l = 12 pf; v pvdd_in = 1.8 v 2 - 10 ns table 57. dynamic characteristics for irq input pin ?continued data are given for t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit table 58. dynamic characteristics for flash memory symbol parameter conditions min typ max unit t prog programming time 1 page (64 bytes); slow clock - - 2.5 ms n endu endurance 200 500 - cycles t ret retention time - 20 - years table 59. dynamic char acteristics for eeprom symbol parameter conditions min typ max unit t prog programming time 1 page (64 bytes) - 2.8 - ms n endu endurance 300 500 - kcycles t ret retention time - 20 - years fig 35. output timing measurement condition for gpio d d d j q g h w i w u PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 68 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.2.4 dynamic characteristics for i 2 c master table 60. dynamic characteristics for gpio1 to gpio21 t amb = ? 40 ? c to +85 ? c symbol parameter conditions min max unit t r rise time c l = 12 pf; pvdd = 1.8 v; slow speed 2.0 10.0 ns c l = 12 pf; pvdd = 1.8 v; fast speed 1.0 3.5 ns c l = 12 pf; pvdd = 3.3 v; slow speed 3.0 10.0 ns c l = 12 pf; pvdd = 3.3 v; fast speed 1.0 3.5 ns t f fall time c l = 12 pf; pvdd = 1.8 v; slow speed 2.0 10.0 ns c l = 12 pf; pvdd = 1.8 v; fast speed 1.0 3.5 ns c l = 12 pf; pvdd = 3.3 v; slow speed 3.0 10.0 ns c l = 12 pf; pvdd = 3.3 v; fast speed 1.0 3.5 ns fig 36. i 2 c-bus pins clock timing d d d 6 ' $ 6 & / w + ' ' $ 7 w + , * + w + ' 6 7 $ w 6 8 6 7 $ w 6 8 ' $ 7 w / 2 : w ' $ w ' $ table 61. timing specificatio n for fast mode plus i 2 c t amb = ? 40 ? c to +85 ? c symbol parameter conditions min max unit f scl scl clock frequency fast mode plus; c b < 100 pf 0 1 mhz t su;sta set-up time for a (repeated) start condition fast mode plus; c b < 100 pf 260 - ns t hd;sta hold time (repeated) start condition fast mode plus; c b < 100 pf 260 - ns t low low period of the scl clock fast mode plus; c b < 100 pf 500 - ns t high high period of the scl clock fast mode plus; c b < 100 pf 260 - ns t su;dat data set-up time fast mode plus; c b < 100 pf 50 - ns t hd;dat data hold time fast mode plus; c b < 100 pf 0 - n s t r(sda) sda rise time fast mode plus; c b < 100 pf - 120 ns t f(sda) sda fall time fast mode plus; c b < 100 pf - 120 ns v hys hysteresis of schmitt trigger inputs fast mode plus; c b < 100 pf 0.1 ?? v pvdd_m_in -v PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 69 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.2.5 dynamic characteristics for spi table 62. timing specification for fast mode i 2 c t amb = ? 40 ? c to +85 ? c symbol parameter conditions min max unit f scl scl clock frequency fast mode; c b < 400 pf 0 400 khz t su;sta set-up time for a (repeated) start condition fast mode; c b < 400 pf 600 - ns t hd;sta hold time (repeated) start condition fast mode; c b < 400 pf 600 - ns t low low period of the scl clock fast mode; c b < 400 pf 1.3 - ? s t high high period of the scl clock fast mode; c b < 400 pf 600 - ns t su;dat data set-up time fast mode; c b < 400 pf 100 - ns t hd;dat data hold time fast mode; c b < 400 pf 0 900 n s t r(sda) sda rise time fast mode plus; c b < 100 pf 30 250 ns t f(sda) sda fall time fast mode plus; c b < 100 pf 30 250 ns v hys hysteresis of schmitt trigger inputs fast mode; c b < 400 pf 0.1 ? v pvdd_in -v fig 37. spi master timing 6 & . & 3 2 / 0 2 6 , 0 , 6 2 7 f \ f o n w ' 6 w ' + w y 4 ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' w k 4 6 & . & 3 2 / ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' 0 2 6 , 0 , 6 2 w ' 6 w ' + ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' w k 4 ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' w y 4 & 3 + $ & 3 + $ d d h PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 70 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.2.6 dynamic characteristics of host interface table 63. dynamic characteristics and timi ng specification for spi master interface symbol parameter conditions min max unit f sck sck frequency controlled by the host 06.78mhz t ds data set-up time 25 - ns t dh data hold time 25 - ns t v(q) data output valid time - 25 ns t h(q) data output hold time - 25 ns dynamic characteristics for spi_sclk, spim_nss, spim_mosi t f fall time c l = 12 pf; high speed; v pvdd_in = 3.3 v 1 3.5 ns c l = 12 pf; slow speed; v pvdd_in = 3.3 v 3 10 ns t r rise time c l = 12 pf; high speed; v pvdd_in = 3.3 v 1 3.5 ns c l = 12 pf; slow speed; v pvdd_in = 3.3 v 3 10 ns t f fall time c l = 12 pf; high speed; v pvdd_in = 1.8 v 1 3.5 ns c l = 12 pf; slow speed; v pvdd_in = 1.8 v 2 10 ns t r rise time c l = 12 pf; high speed; v pvdd_in = 1.8 v 1 3.5 ns c l = 12 pf; slow speed; v pvdd_in = 1.8 v 2 10 ns fig 38. i 2 c-bus pins clock timing 6 ' $ 6 & / d d d w + ' ' $ 7 w + , * + w + ' 6 7 $ w 6 8 6 7 $ w 6 8 ' $ 7 w / 2 : w ' $ w ' $ table 64. timing specification for i2c high speed t amb = ? 40 ? c to +85 ? c symbol parameter conditions min max unit f scl clock frequency high speed; c b < 100 pf 0 3.4 mhz t su;sta set-up time for a (repeated) start condition high speed; c b < 100 pf 160 - ns t hd;sta hold time (repeated) start condition high speed; c b < 100 pf 160 - ns t low low period of the scl clock high speed; c b < 100 pf 160 - ns t high high period of the scl clock high speed; c b < 100 pf 60 - n s t su;dat data set-up time high speed; c b < 100 pf 10 - ns t hd;dat data hold time high speed; c b < 100 pf 0 - ? s PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 71 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller t r(sda) sda rise time high speed; c b < 100 pf 10 80 ns t f(sda) sda fall time high speed; c b < 100 pf 10 80 ns v hys hysteresis of schmitt trigger inputs high speed; c b < 100 pf 0.1 ? v pvdd_in -v table 64. timing specification for i2c high speed t amb = ? 40 ? c to +85 ? c symbol parameter conditions min max unit table 65. dynamic characteristics for the i 2 c slave interface : atx_b used as i 2 c_sda, atx_a used as i 2 c_scl symbol parameter conditions min typ max unit t f fall time c l = 100 pf, r pull-up = 2 k, standard and fast mode 30 - 250 ns c l = 100 pf, r pull-up = 1 k, high speed 10 - 80 ns t r rise time c l = 100 pf, r pull-up = 2 k, standard and fast mode 30 - 250 ns c l = 100 pf, r pull-up = 1 k, high speed 10 - 100 ns fig 39. spi slave timings 6 & . & 3 2 / 0 2 6 , 0 , 6 2 7 f \ f o n w ' 6 w ' + w y 4 ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' w k 4 6 & . & 3 2 / ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' 0 2 6 , 0 , 6 2 w ' 6 w ' + w y 4 ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' w k 4 ' $ 7 $ 9 $ / , ' ' $ 7 $ 9 $ / , ' & 3 + $ & 3 + $ d d h PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 72 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] c l =12 pf maximum. table 66. dynamic characteristics for spi slave interface symbol parameter conditions min max unit f sck sck frequency controlled by the host 07mhz t ds data set-up time 25 - ns t dh data hold time 25 - ns t v(q) data output valid time - 25 ns t h(q) data output hold time - 25 ns table 67. dynamic characteristics fo r spi slave interface: atx_c as spi_miso symbol parameter conditions min typ max unit t f fall time c l = 12 pf; high speed; v pvdd_in = 3.3 v 1- 3.5ns c l = 12 pf; slow speed; v pvdd_in = 3.3 v 3- 10ns t r rise time c l = 12 pf; high speed; v pvdd_in = 3.3 v 1- 3.5ns c l = 12 pf; slow speed; v pvdd_in = 3.3 v 3- 10ns t f fall time c l = 12 pf; high speed; v pvdd_in = 1.8 v 1- 3.5ns c l = 12 pf; slow speed; v pvdd_in = 1.8 v 2- 10ns t r rise time c l = 12 pf; high speed; v pvdd_in = 1.8 v 1- 3.5ns c l = 12 pf; slow speed; v pvdd_in = 1.8 v 2- 10ns table 68. dynamic character istics for hsuart atx_ as hsu_tx, atx_ as hsu_rts symbol parameter conditions [1] min typ max unit t f fall time high speed; v pvdd_in = 3.3 v 1 - 3.5 ns slow speed; v pvdd_in = 3.3 v 3 - 10 ns t r rise time high speed; v pvdd_in = 3.3 v 1 - 3.5 ns slow speed; v pvdd_in = 3.3 v 3 - 10 ns t f fall time high speed; v pvdd_in = 1.8 v 1 - 3.5 ns slow speed; v pvdd_in = 1.8 v 2 - 10 ns t r rise time high speed; v pvdd_in = 1.8 v 1 - 3.5 ns slow speed; v pvdd_in = 1.8 v 2 - 10 ns PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 73 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 13.2.7 clock dynamic characteristics [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c) with nominal supply voltages. table 69. dynamic characteristics for usb interface c l = 50 pf; r pu = 1.5 k ? on d+ to vbus symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 4 - 20 ns t f fall time 10 % to 90 % 4 - 20 ns t frfm differential rise and fall time matching t r / t f - - 109 % v crs output signal crossover voltage 1.3 - 2 v t feopt source se0 interval of eop t = 25 c; see figure 40 160 - 175 ns t fdeop source jitter for diff erential transition to se0 transition t = 25 c; see figure 40 ? 2- +5ns t jr1 receiver jitter to next transition t = 25 c ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 %; t = 25 c ? 9- +9ns t feopr receiver se0 interval of eop must accept as eop; see figure 40 82 - - ns fig 40. usb interface differential data-to -eop transition skew and eop width d d e 7 3 ( 5 , 2 ' g l i i h u h q w l d o g d w d o l q h v f u r v v r y h u s r l q w v r x u f h ( 2 3 z l g w k w ) ( 2 3 7 u h f h l y h u ( 2 3 z l g w k w ( 2 3 5 w ( 2 3 5 f u r v v r y h u s r l q w h [ w h q g h g g l i i h u h q w l d o g d w d w r 6 ( ( 2 3 v n h z q ? 7 3 ( 5 , 2 ' w ) ' ( 2 3 table 70. dynamic characteristics for internal oscillators t amb = ? 40 ? c to +80 ? c symbol parameter [1] conditions min typ [2] max unit low frequency oscillator f osc(int) internal oscillator frequency v ddp(vbus) = 3.3 v 300 365 400 khz high frequency oscillator f osc(int) internal oscillator frequency v ddp(vbus) = 3.3 v 18 20 22 mhz PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 74 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c) with nominal supply voltages. 13.2.8 dynamic characteristics for power supply 13.2.9 dynamic characteristics for boot and reset 13.2.10 dynamics characteristics for power mode [1] wake-up timings are measured from the wake-up event to the poi nt in which the user application code reads the first instruct ion. 13.2.11 dynamic characteristics for contact interface table 71. dynamic characteristics for pll t amb = ? 40 ? c to +80 ? c symbol parameter [1] conditions min typ [2] max unit ? f frequency deviation deviation added to clk_xtal1 frequency on rf frequency generated using pll ? 50 - 50 ppm table 72. dynamic characteristics for power supply symbol parameter conditions min typ max unit dc-to-dc intern al oscillator f osc(int) internal oscillator frequency dc-to-dc converter - 3.39 - mhz table 73. dynamic characteristics for boot and reset symbol parameter conditions min typ max unit t wl(rst_n) rst_n low pulse width time 10 - - ? s t boot boot time external pvdd supply; supply is stable at reset --320 s internal pvdd_ldo supply; supply is stable at reset --2.2 m s table 74. power modes - wake-up timings symbol parameter conditions min typ max unit t wake wake-up time stand-by mode [1] --500 ? s suspend mode [1] --150 ? s table 75. dynamic characteristics for contact interface symbol parameter conditions min typ max unit data lines (pins io, aux1, aux2) f data data rate on data lines - - 1.5 mbps t r(i) input rise time from v il maximum to v ih minimum --1.2 ? s t f(i) input fall time from v il maximum to v ih minimum --1.2 ? s t r(o) output rise time c l < = 80 pf; 10 % to 90 % from 0 to v cc --0.1 ? s t f(o) output fall time c l < = 80 pf; 10 % to 90 % from 0 to v cc --0.1 ? s PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 75 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller [1] the transition time and duty factor definitions are shown in figure 41 . t w(pu) pull-up pulse width - 295 - ns reset output to the card t r rise time c l = 100 pf - - 0.1 ? s t f fall time c l = 100 pf - - 0.1 ? s clock output to the card (clk) t r rise time c l =30pf; f clk = 10 mhz [1] --8ns t r rise time c l =30pf; f clk = 5 mhz [1] --16ns t f fall time c l =30pf; f clk = 10 mhz [1] --8ns t f fall time c l =30pf; f clk = 5 mhz [1] --16ns f clk frequency on pin clk operational 0 - 13.56 mhz ? duty cycle c l =30pf [1] 45 - 55 % sr slew rate rise and fall; c l =30pf; v cc =+5 v 0.2 - - v/ns rise and fall; c l =30pf; v cc =+3 v 0.12 - - v/ns rise and fall; c l =30pf; v cc = +1.8 v 0.072 - - v/ns presn t deb debounce time on pin presn - 6 - ms timings t act activation time see figure 9 ; t = 25 c 11 - 22 ms t deact deactivation time see figure 10 ; t = 25 c 60 100 250 ? s table 75. dynamic characteristics for contact interface ?continued symbol parameter conditions min typ max unit fig 41. definition of output and input transition times i f h w u w i w w 9 2 + 9 2 + 9 2 / 9 2 / PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 76 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 14. marking 14.1 package marking drawing table 76. marking codes type number marking code pn7462 line a pn7462au-00 line b diffusion batch id, assembly sequence id line c characters: diffusion and assembly location, date code, product version (indicated by mask version), product life cycle status. this line includes the following elements at 8 positions: 1. diffusion center code: z 2. assembly center code: s 3. rhf-2006 indicator: d ?dark green? 4. year code (y) 1 5. year code (y) 2 6. week code (w) 1 7. week code (w) 2 8. hw version line d empty line e empty fig 42. marking pn7462 in hvqfn64 d d d $ % & ' ( 7 h u p l q d o l q g h [ d u h d PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 77 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 15. package outline fig 43. package outline hvqfn64 5 h i h u h q f h v 2 x w o l q h y h u v l r q ( x u r s h d q s u r m h f w l r q , v v x h g d w h , ( & - ( ' ( & - ( , 7 $ 6 2 7 v r w b s r 8 q l w p p p d [ q r p p l q $ ' l p h q v l r q v 1 r w h 3 o d v w l f r u p h w d o s u r w u x v l r q v r i p p p d [ l p x p s h u v l g h d u h q r w l q f o x g h g + 9 4 ) 1 s o d v w l f w k h u p d o h q k d q f h g y h u \ w k l q t x d g i o d w s d f n d j h q r o h d g v w h u p l q d o v e r g \ [ [ p p 6 2 7 $ e f ' ' k ' v y z \ \ ' w ( ( k ( v ( w h h h / / / p p v f d o h w h u p l q d o l q g h [ d u h d % $ ' ( & \ & \ ; g h w d l o ; $ f $ ' k ' v ' w ( k ( v ( w / / / e h h h h h h $ & % y & z w h u p l q d o l q g h [ d u h d PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 78 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller fig 44. footprint information for reflow soldering of hvqfn64 v r o g h u o d q g v r o g h u u h v l v w r s h q l q j v r o g h u o d q g s o x v v r o g h u s d v w h 5 h f r p p h q g h g v w h q f l o w k l f n q h v v p p v r o g h u s d v w h g h s r v l w ' l p h q v l r q v l q p p $ \ % [ 6 / \ 6 3 [ 6 3 \ 6 3 \ w r w 3 % \ 6 / [ 6 3 [ w r w & ' * [ * \ + [ + \ $ [ , v v x h g d w h v r w b i u 6 2 7 ) r r w s u l q w l q i r u p d w l r q i r u u h i o r z v r o g h u l q j r i + 9 4 ) 1 s d f n d j h r f f x s l h g d u h d 6 / [ % [ $ [ 6 / \ % \ $ \ * \ + \ & * [ + [ ' 3 6 3 [ 6 3 [ w r w 6 3 \ w r w 6 3 \ ? g u l o o h g y l d v [ g h w d l o ; ; PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 79 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 16. packing information moisture sensitivity level (msl) evaluation has been performed according to jedec j-std-020c. msl for this package is level 3 which means 260 ? c pb-free convection reflow maximum temperature peak. dry packing is required with following floor conditions: 168 hours out of bag floor life at maximum ambient temperature 30 ? c/60 % rh. for information on packing, refer to the pip re lating to this produc t at http://www.nxp.com. 17. abbreviations table 77. abbreviations acronym description adc analog to digital convertor alm active load modulation ask amplitude shift keying bpsk binary phase shift keying clif contactless interface ct contact interface crc cyclic redundancy check dpc dynamic power control eeprom electrically erasable programmable read-only memory gpio general-purpose input output i 2 c inter-interchanged circuit ic integrated circuit iap in-application programming isp in-system programming ldo low dropout lpcd low-power card detection nfc near field communication nrz non-return to zero nvic nested vectored interrupt controller p2p peer-to-peer pll phase locked loop plm passive load modulation spi serial peripheral interface swd serial wire debug uart universal asynchronous receiver transmitter usb universal serial bus PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 80 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 18. revision history table 78. revision history document id release date data sheet status change notice supersedes PN746X_736x v.3.1 20160405 product data sheet - PN746X_736x v.3.0 modifications: ? descriptive title updated ? section 1 ? general description ? : updated PN746X_736x v.3.0 20160330 product data sheet - - PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 81 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 82 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 19.4 licenses 19.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. mifare ? is a trademark of nxp b.v. icode and i-code ? are trademarks of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with nfc technology purchase of an nxp semiconductors ic that complies with one of the near field communication (nfc) standards iso/iec 18092 and iso/iec 21481 does not convey an implied license unde r any patent right infringed by implementation of any of those standards. purchase of nxp semiconductors ic does not include a license to any nxp patent (or other ip right) covering combinations of those products with other products, whether hardware or software. purchase of nxp ics with iso/iec 14443 type b functionality this nxp semiconductors ic is iso/iec 14443 type b software enabled and is licensed under innovatron?s contactless card patents license for iso/iec 14443 b. the license includes the right to use the ic in systems and/or end-user equipment. ratp/innovatron technology PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 83 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 21. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .4 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .5 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 4. interrupt sources . . . . . . . . . . . . . . . . . . . . . . .13 table 5. pin description for host interface . . . . . . . . . . .17 table 6. hsuart baudrates . . . . . . . . . . . . . . . . . . . . .18 table 7. i 2 c interface addressing . . . . . . . . . . . . . . . . . .18 table 8. spi configuration . . . . . . . . . . . . . . . . . . . . . . .19 table 9. communication overview for iso/iec 14443 a/mifare reader/writer . . . . .26 table 10. communication overview for iso/iec 14443 b reader/writer . . . . . . . . . . . .27 table 11. communication overview for felica reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 12. communication overview for iso/iec 15693 reader/writer reader to label . . . . . . . . . . . . . . .28 table 13. communication overview for iso/iec 15693 reader/writer label to reader . . . . . . . . . . . . . .29 table 14. communication overview for active communication mode . . . . . . . . . . . . . . . . . . . .30 table 15. communication overview for passive communication mode . . . . . . . . . . . . . . . . . . . .31 table 16. iso/iec14443 a card operation mode . . . . . . .31 table 17. framing and coding overview. . . . . . . . . . . . . .31 table 18. timer characteristics. . . . . . . . . . . . . . . . . . . . .35 table 19. crystal requirements. . . . . . . . . . . . . . . . . . . . .38 table 20. scldo and dc-to-dc converter modes . . . . .42 table 21. threshold configuration for voltage monitor . . .45 table 22. reset sources. . . . . . . . . . . . . . . . . . . . . . . . . .46 table 23. power supply connection . . . . . . . . . . . . . . . . .47 table 24. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .53 table 25. limiting values for gpio1 to gpio12. . . . . . . .53 table 26. limiting values for i 2 c master pins (i2cm_sda, i2cm_scl) . . . . . . . . . . . . . . . . . . . .53 table 27. limiting values for spi master pins ( spim_nss, spim_miso, spim_mosi and spi_clk) . . . . . . . . .54 table 28. limiting values for host interfaces atx_a, atx_b, atx_c, atx _d in all configurations (usb, hsuart, spi and i 2 c). . . . . . . . . . . . . .54 table 29. limiting values for crystal oscillator . . . . . . . . .54 table 30. limiting values for power supply . . . . . . . . . . .54 table 31. limiting values for contact interface . . . . . . . . .54 table 32. protection and limitat ions for contact interface .54 table 33. limiting values for rf interface . . . . . . . . . . . .55 table 34. operating conditions . . . . . . . . . . . . . . . . . . . .55 table 35. thermal characteristics . . . . . . . . . . . . . . . . . .55 table 36. static characteristics for rst_n input pin . . . .56 table 37. static characteristics for irq input pin . . . . . . .56 table 38. static characteristics for dwl_req . . . . . . . . .56 table 39. static characteristics for gpio1 to gpio21 . . .56 table 40. static characteristics for i 2 cm_sda, i 2 cm_scl - s . . . . . . . . . . . . . . .57 table 41. static characteristics for spim_mosi. . . . . . . .58 table 42. static characteristics for spim_nss. . . . . . . . .58 table 43. static characteristics for spim_miso. . . . . . . .58 table 44. static characteristics for spi_sclk . . . . . . . . .58 table 45. static characteristics for atx_ used as spi_nss, atx_ used as i 2 cadr0, atx_ used as spi_sck, atx_ used as spi_mosi . . . . . . . . . . . . . . . . 58 table 46. static characteristics of atx_ used as i 2 csda, atx_ used as i 2 cscl . . . . . . . . . . . . . . . . . . . 59 table 47. static characteristics of atx_ used as spimiso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 48. usb characteristics . . . . . . . . . . . . . . . . . . . . . 59 table 49. static characteristics of hsu_tx and hsu rts pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 50. static characteristics of hsu_rx, hsu_cts . 60 table 51. static characteristics of xtal pin (xtal1, xtal2) . . . . . . . . . . . . . . . . . . . . . . . . 60 table 52. static characteristics for power supply . . . . . . 61 table 53. static characteristics for voltage monitors . . . . 63 table 54. static characteristics for power modes . . . . . 64 table 55. static characteristics for contact interface . . . . 64 table 56. static characteristics for rf interface . . . . . . . 66 table 57. dynamic characteristi cs for irq input pin . . . . 66 table 58. dynamic characteristics for flash memory . . . 67 table 59. dynamic characteristics for eeprom . . . . . . 67 table 60. dynamic characteri stics for gpio1 to gpio21 68 table 61. timing specification for fast mode plus i 2 c . . . 68 table 62. timing specification for fast mode i 2 c . . . . . . . 69 table 63. dynamic characteristics and timing specification for spi master interface . . . . . . . 70 table 64. timing specification for i2c high speed . . . . . . 70 table 65. dynamic characteristics for the i 2 c slave interface : atx_b used as i 2 c_sda, atx_a used as i 2 c_scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 66. dynamic characteristics for spi slave interface72 table 67. dynamic characteristics for spi slave interface: atx_c as spi_miso . . . . . . . . . . . . . . . . . . . . 72 table 68. dynamic characteristics for hsuart atx_ as hsu_tx, atx_ as hsu_rts . . . . . . . . . . . . . 72 table 69. dynamic characteristi cs for usb interface. . . . 73 table 70. dynamic characteristics for internal oscillators 73 table 71. dynamic characteristics for pll . . . . . . . . . . . 74 table 72. dynamic characteristics for power supply . . . . 74 table 73. dynamic characteristics for boot and reset . . . 74 table 74. power modes - wake-up timings . . . . . . . . . . . 74 table 75. dynamic characteristics for contact interface . 74 table 76. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 77. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 78. revision history . . . . . . . . . . . . . . . . . . . . . . . . 80 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 84 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 22. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 fig 2. pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7 fig 3. flash memory mapping . . . . . . . . . . . . . . . . . . . .10 fig 4. eeprom memory mapping. . . . . . . . . . . . . . . . .10 fig 5. sram memory mapping . . . . . . . . . . . . . . . . . . . 11 fig 6. pn7462 memory map . . . . . . . . . . . . . . . . . . . . .12 fig 7. apb memory map . . . . . . . . . . . . . . . . . . . . . . . .13 fig 8. v ddp(vbus) , supported contact cards classes, and card deactivation. . . . . . . . . . . . . . . . . . . . . .21 fig 9. contact interface - activation sequence. . . . . . . .23 fig 10. deactivation sequence for contact interface . . . .24 fig 11. iso/iec 14443 a/mifare read/write mode communication diagram. . . . . . . . . . . . . . . . . . . .26 fig 12. data coding and framing according to iso/iec 14443 a card response . . . . . . . . . . . . .26 fig 13. iso/iec 14443 b read/write mode communication diagram. . . . . . . . . . . . . . . . . . . .27 fig 14. felica read/write communication diagram. . . . . .27 fig 15. multiple reception cycles - data format . . . . . . . .28 fig 16. iso/iec 15693 read/write mode communication diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 fig 17. data coding according to iso/iec 15693 standard mode reader to label . . . . . . . . . . . . . . .29 fig 18. active communication mode . . . . . . . . . . . . . . . .30 fig 19. passive communication mode . . . . . . . . . . . . . . .30 fig 20. communication in card emulation of nfc passive target. . . . . . . . . . . . . . . . . . . . . . . . . . . .32 fig 21. pn7462 output driver . . . . . . . . . . . . . . . . . . . . . .33 fig 22. receiver block diagram . . . . . . . . . . . . . . . . . . . .34 fig 23. clocks and ip overview . . . . . . . . . . . . . . . . . . . .37 fig 24. crystal oscillator connection . . . . . . . . . . . . . . . .37 fig 25. pn7462 ldos and power pins overview . . . . . . .40 fig 26. powering up the pn7462 microcontroller . . . . . .48 fig 27. powering up the contactless interface using a single power supply . . . . . . . . . . . . . . . . . . . . .49 fig 28. powering up the contactless interface using an external rf transmitter supply . . . . . . . . . . . .49 fig 29. powering up the contact interface . . . . . . . . . . . .50 fig 30. contact interface power supply connection when contact interface is not used. . . . . . . . . . . .51 fig 31. usb interface on a bus-powered device . . . . . . .51 fig 32. connecting the contact interface . . . . . . . . . . . . .52 fig 33. connection of contact interface when not used . .52 fig 34. rf interface - example of connection to an antenna. . . . . . . . . . . . . . . . . . . . . . . . . . . .53 fig 35. output timing measur ement condition for gpio .67 fig 36. i 2 c-bus pins clock timing . . . . . . . . . . . . . . . . . . .68 fig 37. spi master timing . . . . . . . . . . . . . . . . . . . . . . . .69 fig 38. i 2 c-bus pins clock timing . . . . . . . . . . . . . . . . . . .70 fig 39. spi slave timings . . . . . . . . . . . . . . . . . . . . . . . . .71 fig 40. usb interface differential data-to-eop transition skew and eop width . . . . . . . . . . . . . . . . . . . . . .73 fig 41. definition of output a nd input transition times . . .75 fig 42. marking pn7462 in hvqfn64. . . . . . . . . . . . . . .76 fig 43. package outline hvqfn64 . . . . . . . . . . . . . . . . .77 fig 44. footprint information for reflow soldering of hvqfn64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 PN746X_736x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights reserved. product data sheet company public rev. 3.1 ? 5 april 2016 369231 85 of 86 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 ordering information . . . . . . . . . . . . . . . . . . . . . 5 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 functional description . . . . . . . . . . . . . . . . . . . 9 8.1 arm cortex-m0 microcontroller . . . . . . . . . . . . 9 8.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1 on-chip flash programming memory . . . . . . . . 9 8.2.1.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.2.2.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . 10 8.2.3 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.2.3.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . 11 8.2.4 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.3 nested vectored interrupt controller (nvic) . 13 8.3.1 nvic features . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.3.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13 8.4 gpios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4.1 gpio features. . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4.2 gpio configuration . . . . . . . . . . . . . . . . . . . . . 15 8.4.3 gpio interrupts. . . . . . . . . . . . . . . . . . . . . . . . 15 8.5 crc engine 16/32 bits . . . . . . . . . . . . . . . . . . 15 8.6 random number generator (rng) . . . . . . . . 16 8.7 master interfaces . . . . . . . . . . . . . . . . . . . . . . 16 8.7.1 i 2 c master interface . . . . . . . . . . . . . . . . . . . . 16 8.7.1.1 i 2 c features. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.7.2 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.7.2.1 spi features . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.8 host interfaces . . . . . . . . . . . . . . . . . . . . . . . . 17 8.8.1 high-speed uart. . . . . . . . . . . . . . . . . . . . . . 17 8.8.2 i 2 c host interface controller . . . . . . . . . . . . . . 18 8.8.2.1 i 2 c host interface features . . . . . . . . . . . . . . . 18 8.8.3 spi host/slave interface . . . . . . . . . . . . . . . . . 19 8.8.3.1 spi host interface features . . . . . . . . . . . . . . . 19 8.8.4 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8.4.1 full speed usb device controller . . . . . . . . . . 19 8.9 contact interface. . . . . . . . . . . . . . . . . . . . . . . 20 8.9.1 contact interfac e features and benefits . . . . . 20 8.9.2 voltage supervisor . . . . . . . . . . . . . . . . . . . . . 21 8.9.3 clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.9.4 i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.9.5 vcc regulator . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.9.6 activation sequence . . . . . . . . . . . . . . . . . . . . 23 8.9.7 deactivation sequence . . . . . . . . . . . . . . . . . . 23 8.9.8 i/o auxiliary - connecting tda slot extender . 24 8.10 contactless interface - 13.56 mhz . . . . . . . . . 25 8.10.1 rf functionality . . . . . . . . . . . . . . . . . . . . . . . . 25 8.10.1.1 iso/iec14443 a/mifare functionality. . . . . . 25 8.10.1.2 iso/iec14443 b functionality . . . . . . . . . . . . 27 8.10.1.3 felica functionality. . . . . . . . . . . . . . . . . . . . . 27 8.10.1.4 iso/iec 15693 functionality. . . . . . . . . . . . . . 28 8.10.1.5 iso/iec18000-3 mode 3 functionality . . . . . . 29 8.10.1.6 nfcip-1 modes . . . . . . . . . . . . . . . . . . . . . . . 29 8.10.2 low-power card detection (lpcd) . . . . . . . . 32 8.10.3 active load modulation (alm). . . . . . . . . . . . 32 8.10.4 contactless interface . . . . . . . . . . . . . . . . . . . 33 8.10.4.1 transmitter (tx) . . . . . . . . . . . . . . . . . . . . . . . 33 8.10.4.2 receiver (rx) . . . . . . . . . . . . . . . . . . . . . . . . 33 8.10.5 dynamic power control (d pc) . . . . . . . . . . . 35 8.11 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.11.1 features of timer 0 and timer 1 . . . . . . . . . . . 35 8.11.2 features of timer 2 and timer 3 . . . . . . . . . . . 36 8.12 system tick timer . . . . . . . . . . . . . . . . . . . . . . 36 8.13 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 36 8.14 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.14.1 quartz oscillator (27.12 mhz) . . . . . . . . . . . . 37 8.14.2 usb pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.14.3 high frequency oscillator (hfo). . . . . . . . . . 38 8.14.4 low frequency oscillator (lfo) . . . . . . . . . . 38 8.14.5 clock configuration and clock gating . . . . . . . 38 8.15 power management. . . . . . . . . . . . . . . . . . . . 39 8.15.1 power supply sources . . . . . . . . . . . . . . . . . . 39 8.15.2 pn7462 power management unit (pmu) . . . 39 8.15.2.1 main ldo. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.15.2.2 pvdd_ldo . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.15.2.3 contact interface - scldo ldo . . . . . . . . . . 41 8.15.2.4 contact interface dc-to-dc converter . . . . . . 41 8.15.2.5 vcc ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.15.2.6 txldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.15.3 power modes . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.15.3.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.15.3.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . 43 8.15.3.3 suspend mode. . . . . . . . . . . . . . . . . . . . . . . . 43 8.15.3.4 wake-up from standby mode and suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.15.3.5 hard power-down (hpd) mode. . . . . . . . . . . 44 8.15.4 voltage monitoring . . . . . . . . . . . . . . . . . . . . . 45 8.15.4.1 vbus monitor . . . . . . . . . . . . . . . . . . . . . . . . 45 8.15.4.2 vbusp monitor . . . . . . . . . . . . . . . . . . . . . . . 45 8.15.4.3 pvdd ldo supply monitor . . . . . . . . . . . . . . 45 8.15.5 temperature sensor . . . . . . . . . . . . . . . . . . . . 45 8.16 system control . . . . . . . . . . . . . . . . . . . . . . . . 46 8.16.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.16.2 brown-out detection (bod ) . . . . . . . . . . . . . 46 8.16.3 apb interface and ahb-lite. . . . . . . . . . . . . . 46 8.16.4 external interrupt s . . . . . . . . . . . . . . . . . . . . . 46 8.17 swd debug interface. . . . . . . . . . . . . . . . . . . 47 8.17.1 swd interface features . . . . . . . . . . . . . . . . . 47 9 application design-in information. . . . . . . . . 47 9.1 power supply connection . . . . . . . . . . . . . . . . 47 9.1.1 powering up the microcon troller . . . . . . . . . . 48 9.1.2 powering up the contactless interface . . . . . . 48 9.1.3 powering up the contact interface . . . . . . . . . 50 nxp semiconductors PN746X_736x nfc cortex-m0 microcontroller ? nxp semiconductors n.v. 2016. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 5 april 2016 369231 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 9.2 connecting the usb interface . . . . . . . . . . . . 51 9.3 connecting the contact interface . . . . . . . . . . 52 9.4 connecting the rf interface . . . . . . . . . . . . . . 53 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 53 11 recommended operating conditions. . . . . . . 55 12 thermal characteristics . . . . . . . . . . . . . . . . . 55 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.1 static characteristics . . . . . . . . . . . . . . . . . . . . 56 13.1.1 gpio static characteristics . . . . . . . . . . . . . . . 56 13.1.2 static characteristics for i 2 c master . . . . . . . . 57 13.1.3 static characteristics for spi master . . . . . . . . 58 13.1.4 static characteristics for host interface . . . . . . 58 13.1.5 clock static characteristics . . . . . . . . . . . . . . . 60 13.1.6 static characteristics - power supply. . . . . . . . 61 13.1.7 static characteristics for power modes . . . . . . 64 13.1.8 static characteristics for contact interface . . . 64 13.1.9 static characteristics rf interface . . . . . . . . . 66 13.2 dynamic characteristics . . . . . . . . . . . . . . . . . 66 13.2.1 flash memory dynamic characteristics. . . . . . 67 13.2.2 eeprom dynamic characteristics . . . . . . . . . 67 13.2.3 gpio dynamic characteristics . . . . . . . . . . . . 67 13.2.4 dynamic char acteristics for i 2 c master . . . . . 68 13.2.5 dynamic characteristics for spi . . . . . . . . . . . 69 13.2.6 dynamic characteristics of host interface . . . . 70 13.2.7 clock dynamic characteristics . . . . . . . . . . . . 73 13.2.8 dynamic characteristics for power supply . . . 74 13.2.9 dynamic characteristics for boot and reset. . . 74 13.2.10 dynamics characteristics for power mode . . . 74 13.2.11 dynamic characteristics for contact interface . 74 14 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.1 package marking drawing . . . . . . . . . . . . . . . 76 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 77 16 packing information . . . . . . . . . . . . . . . . . . . . 79 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . 80 19 legal information. . . . . . . . . . . . . . . . . . . . . . . 81 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 81 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 19.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 19.5 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 82 20 contact information. . . . . . . . . . . . . . . . . . . . . 82 21 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 22 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 23 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 |
Price & Availability of PN746X
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